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Occasional Contributor

5 years ago

PCI Express Hard IP on Cyclone 10GX: BARs using I/O space and debug questions

I have a design using the hard PCIe core in a Cyclone 10 GX. First time we're using it. Quartus Prime Pro 19.3. Two questions: 1) It appears to be impossible to set any of the BAR registers to ...

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Frequent Contributor

5 years ago

Hi ,

Keeping the post in public.

May I know which PCIEe IP you are using is it Avalon MM Avalon ST.

NWein
Occasional Contributor
5 years ago
It's Avalon MM.
- Rahul_S_Intel1
  Frequent Contributor
  5 years ago
  Kindly find the inline answers for your question.
  
  Question no:1
  
  It is not possible to se the I/O address space in Cyclone 10 GX and for your info the I/O address space is only supported in Legacy endpoint . The Legacy endpoint is only supported in certain variants of Arria 10 devices Avalon ST configuration.
  
  Below is the error you will get from qsys when you select the I/O address space.
  
  Error: pcie_a10_hip_0: The current value "I/O address space" for parameter "Type" (bar0_type_hwtcl) is invalid. Possible valid values are: "Disabled" "64-bit prefetchable memory" "32-bit non-prefetchable memory". The parameter value is invalid under these current parameter settings: "Port type" (port_type_hwtcl)="Native endpoint". Rule(s): bar0_type.
  
  Question:2
  
  For debugging the PCIe , we have an step by step documentation, in the below link. If you could not able to access the link kindly let me know.
  
  https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html
  - Rahul_S_Intel1
    Frequent Contributor
    5 years ago
    Hi ,
    
    May I know still you need support