PCI Express Hard IP on Cyclone 10GX: BARs using I/O space and debug questions

Kindly find the inline answers for your question.

Question no:1

It is not possible to se the I/O address space in Cyclone 10 GX and for your info the I/O address space is only supported in Legacy endpoint . The Legacy endpoint is only supported in certain variants of Arria 10 devices Avalon ST configuration.

Below is the error you will get from qsys when you select the I/O address space.

Error: pcie_a10_hip_0: The current value "I/O address space" for parameter "Type" (bar0_type_hwtcl) is invalid. Possible valid values are: "Disabled" "64-bit prefetchable memory" "32-bit non-prefetchable memory". The parameter value is invalid under these current parameter settings: "Port type" (port_type_hwtcl)="Native endpoint". Rule(s): bar0_type.

Question:2

For debugging the PCIe , we have an step by step documentation, in the below link. If you could not able to access the link kindly let me know.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html