Open Core IP time limited source files expired.

You should not need any patch for Quartus 8.0. Your post does not say what exactly you are trying to do, nor does it mention any error messages.

Can you please clarify exactly what you are trying to do?

I was just following one of the tutorials on building system using SOPC builder. When I tried using the programmer it said that the file had a few IP core services which uses hardware evaluation and hence I could not program it into the FPGA.

I am using DE2 kit from Altera and I have not purchased a license.

As soon as I click on the programmer, a dialog box pops up which tells me that the file is time limited.

What device have you chosen? If you chose a device that has programmer support, you should be able to program the FPGA using the OpenCore Plus hardware evaluation feature for any design that contains Altera IP. You do not need to have a license. OpenCore Plus hardware evaluation is time-limited, but as long as your programmer is connected to your board your design should continue working in hardware.

Can you also tell me which IP cores you are using? Perhaps you are using non-Altera IP.

Perhaps you should contact Altera technical support. I would guess that you just need some help getting started.

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I was just following one of the tutorials on building system using SOPC builder. When I tried using the programmer it said that the file had a few IP core services which uses hardware evaluation and hence I could not program it into the FPGA.

I am using DE2 kit from Altera and I have not purchased a license.

As soon as I click on the programmer, a dialog box pops up which tells me that the file is time limited.

--- Quote End ---

You are probably misunderstanding the meaning of the warning messages. The programmer can configure the FPGA with a time-limited SOF.

You should see two warning messages. One is from the assembler. It is telling that it can't generate device programming files. This means it can generate a SOF for configuring the FPGA, but it can't generate a POF for programming a flash device.

The second warning is from the programmer when configuring the FPGA. The warning is telling you that it is a time-limited SOF. This means that the evaluations cores require a permanent link with Quartus programmer, or they would stop working after a certain time.

dear quartuspenguin, thanks a lot! i had the same problem:

Error: Can't generate netlist output files because the file ... is an OpenCore Plus time-limited file

disabled the all EDA tools under EDA Tool Settings --> compilation complete :-)

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Hi Dimo

I have seen this before with opencore / opencore plus.

The problem you are seeing is because you have 3rd party simulation enabled (hence the EDA netlist writer is running, which is where the error is being seen).

Opencore plus does not allow creation of simulation netlists. Try turning this option off under settings->eda tool settings->simultion. (select no simulator)

If this still doesn't work try removing the PCIE.

Cheers

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thank you for your advices, and I try your method ,but it work successfully.However ,I want to ask modelsim for simulation, I can't close the 3rd party simulation , how I can do to solve this problem

Error: Can't generate netlist output files because the file "D:/altera/10.1/quartus/qdesigns/FFT/FFT1/fft-library/asj_fft_wrengen_fft_101.vhd" is an OpenCore Plus time-limited file

Woohoo.. I had the same issue and was wondering! Thanks for the solution QuartusPenguin..

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Hi Dimo

I have seen this before with opencore / opencore plus.

The problem you are seeing is because you have 3rd party simulation enabled (hence the EDA netlist writer is running, which is where the error is being seen).

Opencore plus does not allow creation of simulation netlists. Try turning this option off under settings->eda tool settings->simultion. (select no simulator)

If this still doesn't work try removing the PCIE.

Cheers

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