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AMoha31's avatar
AMoha31
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7 years ago

Not able to generate HDL because of tight clock constraints -Altera DSP builder

I am trying to develop a Simulink model of electric machine with DSP builder advanced blockset. This model will be later used to generate HDL code and loaded into Vector VT System FPGA (Altera Cyclen IV E).

I am able to simulate the system in simulink but when I generate the hardware it says 'Failure to redistribute delay in [IM_Test_User_FPGA] - tight clock constraints'​.

I am using an 80 MHz clock.

Kindly let me know how I can tackle this problem.

Thank You

Athul Mohan

10 Replies

  • AMoha31's avatar
    AMoha31
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    7 years ago
    Hello KYeoh, Please find the details of the software below. MATLAB Version 8.6 (R2015b) Simulink Version 8.6 (R2015b) Altera DSP Builder Advanced Blockset Flow Tools Version 16.1 Build 196 Altera DSP Builder Standard Blockset Version 16.1 Build 196 Quartus Prime 16.1.0.196 ModelSim Intel FPGA Edition version 10.5b Kindly go through the issue and revert. Regards Athul Mohan
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
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    7 years ago

    Hi Athul Mohan,

    MATLAB Version 8.6 (R2015b) is not compatible with the Intel Quartus Prime software version 16.1. It supports MathWorks releases R2015a, R2014b.

    Can you use the latest release of the software, which is v18.1?

    Can you try to reduce the speed and see if you have the same error?

    Thanks.

  • AMoha31's avatar
    AMoha31
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    7 years ago

    ​Hi KYeoh,

    I tried to reduce the clock speed but it gives the same error.

    Once I reduce the clock speed below 20 MHz it gives different error - Failure to redistribute delay in [IM_Test_User_FPGA] - negative cycle.

    Thank You

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
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    7 years ago

    Hi Athul Mohan,

    Can you use the latest release of the software, which is v18.1?

    Thanks

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi Athul Mohan,

    In <Quartus installation directory>/quartus/readme.txt, version 16.1 supports MathWorks releases R2015a, R2014b only. Let me check on this.

    Have you try to reduce the speed to a value less than 80 and more than 20?

    Thanks

  • AMoha31's avatar
    AMoha31
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    7 years ago

    ​Hi KYeoh,

    Yes, between 80 and 20 MHz I am getting the same error - 'Failure to redistribute delay in [IM_Test_User_FPGA] - tight clock constraints

    Thank You

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi Athul Mohan,

    Can you use the latest release of the software and see if the problem persists?

    Thanks.

  • AMoha31's avatar
    AMoha31
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    7 years ago

    ​Hi KYeoh,

    If I have to use the latest version v18.1, then I have to update the MATLAB Simulink to Version R2016b or above. Currently I have license for only MATLAB 2015b.

    Thank You