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AMoha31
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7 years ago

Not able to generate HDL because of tight clock constraints -Altera DSP builder

I am trying to develop a Simulink model of electric machine with DSP builder advanced blockset. This model will be later used to generate HDL code and loaded into Vector VT System FPGA (Altera Cyclen...
AMoha31's avatar
AMoha31
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7 years ago
Hello KYeoh, Please find the details of the software below. MATLAB Version 8.6 (R2015b) Simulink Version 8.6 (R2015b) Altera DSP Builder Advanced Blockset Flow Tools Version 16.1 Build 196 Altera DSP Builder Standard Blockset Version 16.1 Build 196 Quartus Prime 16.1.0.196 ModelSim Intel FPGA Edition version 10.5b Kindly go through the issue and revert. Regards Athul Mohan