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AMoha31
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7 years ago

Not able to generate HDL because of tight clock constraints -Altera DSP builder

I am trying to develop a Simulink model of electric machine with DSP builder advanced blockset. This model will be later used to generate HDL code and loaded into Vector VT System FPGA (Altera Cyclen...
AMoha31's avatar
AMoha31
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7 years ago

​Hi KYeoh,

I tried to reduce the clock speed but it gives the same error.

Once I reduce the clock speed below 20 MHz it gives different error - Failure to redistribute delay in [IM_Test_User_FPGA] - negative cycle.

Thank You