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AMoha31's avatar
AMoha31
Icon for New Contributor rankNew Contributor
7 years ago

Not able to generate HDL because of tight clock constraints -Altera DSP builder

I am trying to develop a Simulink model of electric machine with DSP builder advanced blockset. This model will be later used to generate HDL code and loaded into Vector VT System FPGA (Altera Cyclen...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Athul Mohan,

In <Quartus installation directory>/quartus/readme.txt, version 16.1 supports MathWorks releases R2015a, R2014b only. Let me check on this.

Have you try to reduce the speed to a value less than 80 and more than 20?

Thanks