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AMoha31's avatar
AMoha31
Icon for New Contributor rankNew Contributor
7 years ago

Not able to generate HDL because of tight clock constraints -Altera DSP builder

I am trying to develop a Simulink model of electric machine with DSP builder advanced blockset. This model will be later used to generate HDL code and loaded into Vector VT System FPGA (Altera Cyclen...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Athul Mohan,

MATLAB Version 8.6 (R2015b) is not compatible with the Intel Quartus Prime software version 16.1. It supports MathWorks releases R2015a, R2014b.

Can you use the latest release of the software, which is v18.1?

Can you try to reduce the speed and see if you have the same error?

Thanks.