New ContributorNone of the other write signals get updated even though we have ensured that the waitrequest is low during MSGDMA Simulation
If you could refer to the timing diagram attached, you will see that at t = 960ns a descriptor is issued to the MSGDMA. a few clock cycles later, the read memory mapped master then begins to act upon this request.
The read_address and read_burstcount update correctly, to 0x04000000 and 0x40 respectively for a transfer length of 1KB.
Once the read request goes low, we assert the read_readdatavalid signal using user logic in our test bench.
And at t = 1200ns we see that the write_byteenable and write_writedata also update properly. However, none of the other write signals get updated even though we have ensured that the waitrequest is low.
We have verified that the port mappings are the correct width and direction. We have also tried disconnecting the write_write signal from the UUT and the MSGDMA still pulls it low.
There are warnings like these:
Region: /depth_engine_tb/u0/msgdma_0/dispatcher_internal/the_descriptor_buffers/the_read_command_FIFO/the_dp_ram
# ** Warning: (vsim-3722) simulation/submodules/fifo_with_byteenables.v(128): [TFMPC] - Missing connection for port 'wren_b'.
Any insight into this issue would be greatly appreciated.
