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EDing
New Contributor
New ContributorNone of the other write signals get updated even though we have ensured that the waitrequest is low during MSGDMA Simulation
If you could refer to the timing diagram attached, you will see that at t = 960ns a descriptor is issued to the MSGDMA. a few clock cycles later, the read memory mapped master then begins to act upon...
HBhat2
Contributor
ContributorHi @EDing
# ** Warning: (vsim-3722) simulation/submodules/fifo_with_byteenables.v(128): [TFMPC] - Missing connection for port 'wren_b'.
The above warning related to the module instantiation. Please check the instantiation of fifo_with_byteenables.v module and "wren_b" port might have not connected or always stuck at 0/1.
With Regards,
HPB
