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EDing
New Contributor
New ContributorNone of the other write signals get updated even though we have ensured that the waitrequest is low during MSGDMA Simulation
If you could refer to the timing diagram attached, you will see that at t = 960ns a descriptor is issued to the MSGDMA. a few clock cycles later, the read memory mapped master then begins to act upon...
EDingNew Contributor
New ContributorHi HPB,
When I try to trace down these errors, it all comes down to instantiation within these sub modules of Altera Megafunctions. In this case what appears to be the read signal is missing.
Since these files were output by the Platform Designer software I am hesitant to edit them.
See attached picture.
