None of the other write signals get updated even though we have ensured that the waitrequest is low during MSGDMA Simulation

Hi HPB,

According to the Simulation Flow table, since I am simulating a Platform Designer design, the MSGDMA, then I am to follow the steps referred to Creating a System with Platform Designer. I followed the steps outlined in the Advanced System Design Using Platform Designer: Component & System Simulation Tutorial.

I also tried to follow the suggestions outlined under Scripted Simulation Flow. However, the steps say to generate the simulation files from the IP upgrade window and even though the auto upgrade completed successfully, "Generate Simulation Script for IP" button is unavailable.

Similarly, it is suggested to go to Tools > Generate Simulator Setup Script for IP but that is not visible in my Tools menu.

Moreover, our full Quartus project contains IP and sub modules (like the mac1g) that we do not plan on simulating right now. We can exclude them but I am hoping to find a solution that allows us simulate a sub section of our project.

Suggestions on how to proceed would be appreciated.

Thanks,

Ellen