ymiler
Contributor
4 years agoLVDS SERDES IP
Hi
I use 2 LVDS SERDES IP in my project (TX & RX)
According to your datasheet : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-lvds.pdf page 39 - There is option to configure external PLL instead of the SERDES IP .
I have 2 questions -
1)Do I need to configure for both (RX & TX IP) external IP or I can configure only for 1 of them-according to page 39 - I must configure in both of them
2)Can I connect clock to the external PLL from global dedicated clock pin but not from dedicated SERDES pin?
Thanks
Yishay