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ymiler's avatar
ymiler
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5 years ago

LVDS SERDES IP

Hi I use 2 LVDS SERDES IP in my project (TX & RX) According to your datasheet : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-lvds.pdf page 39 -...
EngWei_O_Intel's avatar
EngWei_O_Intel
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5 years ago

Hi Yishay

RX and TX shall be independent in selecting internal/external PLL mode. Let me know if you seeing otherwise during compilation.

For SERDES usage, it is always recommended to drive the PLL with dedicated clock.

Thanks.

Eng Wei

  • ymiler's avatar
    ymiler
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    5 years ago

    Hi Eng Wei ,

    {Eng Wei} RX and TX shall be independent in selecting internal/external PLL mode {YM} = according to your datasheet(page 39) should to be both external PLL :

    So , Do I need to configure for both (RX & TX IP) external IP

    {Eng Wei} For SERDES usage, it is always recommended to drive the PLL with dedicated clock.{YM} = Your recommended is for input serdes clock or also for TX serdes clock ?

    Yishay Miller

    • EngWei_O_Intel's avatar
      EngWei_O_Intel
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      5 years ago

      Hi Yishay Miller

      The diagram is showing the connectivity we need to have for Tx and Rx if they are configured as external PLL mode, as there are no direct connections between Tx and Rx in the diagram.

      Yup, we shall use dedicated clock for both.

      Thanks.

      Eng Wei