New Contributorhi everyone:
i want to use LPM DIVIDE in max 10, and i use quartus prime 16.1, the clk is 96MHz
but i did not found information about the latency of LPM DIVIDE , so i do not know how many clks should i wait to get the right outputs
New Contributor
this is my lpm divide block
numer unsigned 21 bits
denom unsigned 12 bits
i use signal tab to monitor the latency,
but i find the latency changes from 2clk(20.8ns) to 5clk (52ns)
i want to know the max latency
thanks!
Super ContributorUsually, what we do is use the modelsim to simulate the RTL behavior of the design first.
Then constrain the design and make sure the timing closed.
From there, you should be able to see the latency in the Timing reports.
This latency should not be vary so much. If you look into the modelsim simulation, you will see usually, it take about one cycle of input clock to do the operation.
New Contributori test the latency in signaltab, sometimes is 4 clks.
how to constrain the lpm divide?
Super Contributorwhy don't you attached your design.qar here for us to take a look?
You may take a look this video for constrain a design
https://www.youtube.com/watch?v=hfaiPxl9Z9A
New Contributorhi
this is my project.
i do not know what constraints should i use
multicycle path?
max delay?
thanks!
Super ContributorWhat I try is simulate your design in the rtl simulator vwf files. I dont see any output, can you try it on your side? You can bring out the *vwf files with file -> new -> vwf files.
https://www.youtube.com/watch?v=RU4LU1nokwg
You dont need to set the multicycle path for now, after you make sure your rtl simulation behavior, only you set the multicycle.
Super Contributorany update?
Super ContributorWe do not receive any response from you to the previous reply that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
