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qd0090's avatar
qd0090
Icon for New Contributor rankNew Contributor
5 years ago

LPM DIVIDE latency

hi everyone: i want to use LPM DIVIDE in max 10, and i use quartus prime 16.1, the clk is 96MHz but i did not found information about the latency of LPM DIVIDE , so i do not know how many c...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

What I try is simulate your design in the rtl simulator vwf files. I dont see any output, can you try it on your side? You can bring out the *vwf files with file -> new -> vwf files.


https://www.youtube.com/watch?v=RU4LU1nokwg


You dont need to set the multicycle path for now, after you make sure your rtl simulation behavior, only you set the multicycle.