New Contributor
Super ContributorUsually, what we do is use the modelsim to simulate the RTL behavior of the design first.
Then constrain the design and make sure the timing closed.
From there, you should be able to see the latency in the Timing reports.
This latency should not be vary so much. If you look into the modelsim simulation, you will see usually, it take about one cycle of input clock to do the operation.
New Contributori test the latency in signaltab, sometimes is 4 clks.
how to constrain the lpm divide?
