library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.


entity adc_driver_adc7276 is
    Port ( dcm_96MHz : in  STD_LOGIC;
           reset : in  STD_LOGIC;
				adc_cs : out std_LOGIC;
				adc_sclk: out std_LOGIC;
				sdo : in std_LOGIC;
				adc_data : out std_LOGIC_vector(11 downto 0 );
				get_adc_data_done : out std_LOGIC
				
			  );
end adc_driver_adc7276;

architecture Behavioral of adc_driver_adc7276 is
type state1 is (idle,st0,st0_1,st1,st2);

--------------------------------reg------------------------
signal state1_reg: state1:=idle;
signal S_adc_cs_reg : std_LOGIC:='1';
signal S_adc_sclk_reg : std_LOGIC:='1';
--signal S_sdo_reg : std_LOGIC:='0';
signal  S_count1_reg : unsigned(6 downto 0) :=(others=>'0');
signal  S_adc_data_reg :  std_LOGIC_vector(11 downto 0 ):=(others=>'0');
signal  S_get_adc_data_done_reg: std_LOGIC:='0';
--------------------------------reg------------------------

--------------------------------next------------------------
signal state1_next: state1:=idle;
signal S_adc_cs_next : std_LOGIC:='1';
signal S_adc_sclk_next : std_LOGIC:='1';
signal  S_count1_next : unsigned(6 downto 0) :=(others=>'0');
signal  S_adc_data_next :  std_LOGIC_vector(11 downto 0 ):=(others=>'0');
signal  S_get_adc_data_done_next: std_LOGIC:='0';
--------------------------------next------------------------


begin

process(dcm_96MHz,reset)
begin
	if reset='0' then
		state1_reg<=idle;
		S_adc_cs_reg <='1';
		S_adc_sclk_reg <='1';
		S_count1_reg<=(others=>'0');
		S_adc_data_reg<=(others=>'0');
		S_get_adc_data_done_reg<='0';
		
	elsif rising_edge(dcm_96MHz) then
		state1_reg<=state1_next;
		S_adc_cs_reg <=S_adc_cs_next;
		S_adc_sclk_reg <=S_adc_sclk_next;		
		S_count1_reg<=S_count1_next;
		S_adc_data_reg<=S_adc_data_next;
		S_get_adc_data_done_reg<=S_get_adc_data_done_next;
	end if;
end process;



process(state1_reg,S_adc_cs_reg,S_adc_sclk_reg,S_count1_reg,s_adc_data_reg,sdo)
begin
	state1_next<=state1_reg;
	S_adc_cs_next<=S_adc_cs_reg;
	S_adc_sclk_next<=S_adc_sclk_reg;	
	S_count1_next<=S_count1_reg;
	S_adc_data_next		<=S_adc_data_reg;
	S_get_adc_data_done_next	<='0';
	case state1_reg is 
		when idle =>
			S_adc_cs_next<='1';
			
--			S_count2_next<=(others=>'0');
			S_adc_sclk_next <='1';
			
			if S_count1_reg="1111111" then
				S_count1_next<=(others=>'0');
				state1_next<=st0;
			else
				S_count1_next<=S_count1_reg + 1;
			
			end if;

			
	

		when st0 =>
			S_adc_cs_next<='0';
			state1_next<=st1;
		when st1 =>
			S_adc_sclk_next <= not S_adc_sclk_reg;
			

			if S_count1_reg="00011011" then					--60  simu it 
				S_adc_cs_next<='1';
				S_count1_next<=(others=>'0');
				state1_next<=st2;
				S_get_adc_data_done_next<='1';
			else
				S_count1_next<=S_count1_reg + 1;
				S_adc_cs_next<='0';
			end if;
			
			if S_adc_sclk_reg='1' then			--should test
				S_adc_data_next<=S_adc_data_reg(10 downto 0) & sdo;
			
			end if;
			
		when st2 =>
			if S_count1_reg="0000100" then					-- 
				S_count1_next<=(others=>'0');
				
				state1_next<=st0;
			
			else
				S_count1_next<=S_count1_reg + 1;
			end if;		
			

			
		when others=>
			null;
			
	end case;
	

end process;




adc_cs<=S_adc_cs_reg;
adc_sclk<=S_adc_sclk_reg;	
adc_data<=S_adc_data_reg;
get_adc_data_done	<=S_get_adc_data_done_reg;

end Behavioral;

