library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.


entity input_buff is
    Port ( dcm_96MHz : in  STD_LOGIC;
           reset : in  STD_LOGIC;
			  fpga_in : in  STD_LOGIC;
			  fpga_out : in  STD_LOGIC;
			  
			  );
end top_control;

architecture Behavioral of top_control is
type state1 is (idle,idle0,idle1,st0,st0_1,st1,st2,st3);

--------------------------------reg------------------------
signal state1_reg: state1:=idle;



--------------------------------reg------------------------

--------------------------------next------------------------
signal state1_next: state1:=idle;

--------------------------------next------------------------


begin

process(dcm_96MHz,reset)
begin
	if reset='0' then

	elsif rising_edge(dcm_96MHz) then

	end if;
end process;





process(
)
begin

	

end process;


end Behavioral;

