Fitter report for fs20_01
Wed Sep 16 13:24:07 2020
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Parallel Compilation
  5. Incremental Compilation Preservation Summary
  6. Incremental Compilation Partition Settings
  7. Incremental Compilation Placement Preservation
  8. Pin-Out File
  9. Fitter Resource Usage Summary
 10. Fitter Partition Statistics
 11. Input Pins
 12. Output Pins
 13. Dual Purpose and Dedicated Pins
 14. I/O Bank Usage
 15. All Package Pins
 16. PLL Summary
 17. PLL Usage
 18. I/O Assignment Warnings
 19. Fitter Resource Utilization by Entity
 20. Delay Chain Summary
 21. Pad To Core Delay Chain Fanout
 22. Control Signals
 23. Global & Other Fast Signals
 24. Fitter RAM Summary
 25. Routing Usage Summary
 26. LAB Logic Elements
 27. LAB-wide Signals
 28. LAB Signals Sourced
 29. LAB Signals Sourced Out
 30. LAB Distinct Inputs
 31. I/O Rules Summary
 32. I/O Rules Details
 33. I/O Rules Matrix
 34. Fitter Device Options
 35. Operating Settings and Conditions
 36. Estimated Delay Added for Hold Timing Summary
 37. Estimated Delay Added for Hold Timing Details
 38. Fitter Messages
 39. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2016  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Intel and sold by Intel or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+--------------------------------------------------------------------------------------+
; Fitter Summary                                                                       ;
+------------------------------------+-------------------------------------------------+
; Fitter Status                      ; Successful - Wed Sep 16 13:24:07 2020           ;
; Quartus Prime Version              ; 16.1.0 Build 196 10/24/2016 SJ Standard Edition ;
; Revision Name                      ; fs20_01                                         ;
; Top-level Entity Name              ; fs20_01                                         ;
; Family                             ; MAX 10                                          ;
; Device                             ; 10M08SCM153I7G                                  ;
; Timing Models                      ; Final                                           ;
; Total logic elements               ; 2,546 / 8,064 ( 32 % )                          ;
;     Total combinational functions  ; 1,596 / 8,064 ( 20 % )                          ;
;     Dedicated logic registers      ; 1,609 / 8,064 ( 20 % )                          ;
; Total registers                    ; 1609                                            ;
; Total pins                         ; 44 / 112 ( 39 % )                               ;
; Total virtual pins                 ; 0                                               ;
; Total memory bits                  ; 182,272 / 387,072 ( 47 % )                      ;
; Embedded Multiplier 9-bit elements ; 0 / 48 ( 0 % )                                  ;
; Total PLLs                         ; 1 / 1 ( 100 % )                                 ;
; UFM blocks                         ; 0 / 1 ( 0 % )                                   ;
; ADC blocks                         ; 0                                               ;
+------------------------------------+-------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                                            ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Option                                                                     ; Setting                               ; Default Value                         ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Device                                                                     ; 10M08SCM153I7G                        ;                                       ;
; Minimum Core Junction Temperature                                          ; -40                                   ;                                       ;
; Maximum Core Junction Temperature                                          ; 100                                   ;                                       ;
; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
; Use smart compilation                                                      ; Off                                   ; Off                                   ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
; Enable compact report table                                                ; Off                                   ; Off                                   ;
; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
; SSN Optimization                                                           ; Off                                   ; Off                                   ;
; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
; PCI I/O                                                                    ; Off                                   ; Off                                   ;
; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
; Auto Delay Chains                                                          ; On                                    ; On                                    ;
; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
; Auto Global Clock                                                          ; On                                    ; On                                    ;
; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.12        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  12.0%      ;
+----------------------------+-------------+


+---------------------------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary                                                      ;
+---------------------+---------------------+----------------------------+--------------------------+
; Type                ; Total [A + B]       ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+---------------------+----------------------------+--------------------------+
; Placement (by node) ;                     ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 3402 ) ; 0.00 % ( 0 / 3402 )        ; 0.00 % ( 0 / 3402 )      ;
;     -- Achieved     ; 0.00 % ( 0 / 3402 ) ; 0.00 % ( 0 / 3402 )        ; 0.00 % ( 0 / 3402 )      ;
;                     ;                     ;                            ;                          ;
; Routing (by net)    ;                     ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
;     -- Achieved     ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+---------------------+---------------------+----------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                                                             ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
; sld_hub:auto_hub               ; Auto-generated ; Post-Synthesis    ; N/A                     ; Post-Synthesis         ; N/A                          ; sld_hub:auto_hub               ;
; sld_signaltap:auto_signaltap_0 ; Auto-generated ; Post-Synthesis    ; N/A                     ; Post-Synthesis         ; N/A                          ; sld_signaltap:auto_signaltap_0 ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                                                                     ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Top                            ; 0.00 % ( 0 / 1014 )   ; N/A                     ; Source File       ; N/A                 ;       ;
; sld_hub:auto_hub               ; 0.00 % ( 0 / 219 )    ; N/A                     ; Post-Synthesis    ; N/A                 ;       ;
; sld_signaltap:auto_signaltap_0 ; 0.00 % ( 0 / 2159 )   ; N/A                     ; Post-Synthesis    ; N/A                 ;       ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/output_files/fs20_01.pin.


+--------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                            ;
+---------------------------------------------+----------------------------+
; Resource                                    ; Usage                      ;
+---------------------------------------------+----------------------------+
; Total logic elements                        ; 2,546 / 8,064 ( 32 % )     ;
;     -- Combinational with no register       ; 937                        ;
;     -- Register only                        ; 950                        ;
;     -- Combinational with a register        ; 659                        ;
;                                             ;                            ;
; Logic element usage by number of LUT inputs ;                            ;
;     -- 4 input functions                    ; 480                        ;
;     -- 3 input functions                    ; 738                        ;
;     -- <=2 input functions                  ; 378                        ;
;     -- Register only                        ; 950                        ;
;                                             ;                            ;
; Logic elements by mode                      ;                            ;
;     -- normal mode                          ; 1117                       ;
;     -- arithmetic mode                      ; 479                        ;
;                                             ;                            ;
; Total registers*                            ; 1,609 / 8,597 ( 19 % )     ;
;     -- Dedicated logic registers            ; 1,609 / 8,064 ( 20 % )     ;
;     -- I/O registers                        ; 0 / 533 ( 0 % )            ;
;                                             ;                            ;
; Total LABs:  partially or completely used   ; 203 / 504 ( 40 % )         ;
; Virtual pins                                ; 0                          ;
; I/O pins                                    ; 44 / 112 ( 39 % )          ;
;     -- Clock pins                           ; 3 / 4 ( 75 % )             ;
;     -- Dedicated input pins                 ; 1 / 1 ( 100 % )            ;
;                                             ;                            ;
; M9Ks                                        ; 23 / 42 ( 55 % )           ;
; UFM blocks                                  ; 0 / 1 ( 0 % )              ;
; Total block memory bits                     ; 182,272 / 387,072 ( 47 % ) ;
; Total block memory implementation bits      ; 211,968 / 387,072 ( 55 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 48 ( 0 % )             ;
; PLLs                                        ; 1 / 1 ( 100 % )            ;
; Global signals                              ; 3                          ;
;     -- Global clocks                        ; 3 / 10 ( 30 % )            ;
; JTAGs                                       ; 1 / 1 ( 100 % )            ;
; CRC blocks                                  ; 0 / 1 ( 0 % )              ;
; Remote update blocks                        ; 0 / 1 ( 0 % )              ;
; Oscillator blocks                           ; 0 / 1 ( 0 % )              ;
; Average interconnect usage (total/H/V)      ; 5.3% / 5.0% / 5.7%         ;
; Peak interconnect usage (total/H/V)         ; 10.6% / 10.2% / 11.2%      ;
; Maximum fan-out                             ; 978                        ;
; Highest non-global fan-out                  ; 292                        ;
; Total fan-out                               ; 10881                      ;
; Average fan-out                             ; 2.68                       ;
+---------------------------------------------+----------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics                                                                                                                              ;
+---------------------------------------------+---------------------+--------------------+--------------------------------+--------------------------------+
; Statistic                                   ; Top                 ; sld_hub:auto_hub   ; sld_signaltap:auto_signaltap_0 ; hard_block:auto_generated_inst ;
+---------------------------------------------+---------------------+--------------------+--------------------------------+--------------------------------+
; Difficulty Clustering Region                ; Low                 ; Low                ; Low                            ; Low                            ;
;                                             ;                     ;                    ;                                ;                                ;
; Total logic elements                        ; 826 / 8064 ( 10 % ) ; 154 / 8064 ( 2 % ) ; 1566 / 8064 ( 19 % )           ; 0 / 8064 ( 0 % )               ;
;     -- Combinational with no register       ; 727                 ; 63                 ; 147                            ; 0                              ;
;     -- Register only                        ; 10                  ; 26                 ; 914                            ; 0                              ;
;     -- Combinational with a register        ; 89                  ; 65                 ; 505                            ; 0                              ;
;                                             ;                     ;                    ;                                ;                                ;
; Logic element usage by number of LUT inputs ;                     ;                    ;                                ;                                ;
;     -- 4 input functions                    ; 116                 ; 54                 ; 310                            ; 0                              ;
;     -- 3 input functions                    ; 503                 ; 37                 ; 198                            ; 0                              ;
;     -- <=2 input functions                  ; 197                 ; 37                 ; 144                            ; 0                              ;
;     -- Register only                        ; 10                  ; 26                 ; 914                            ; 0                              ;
;                                             ;                     ;                    ;                                ;                                ;
; Logic elements by mode                      ;                     ;                    ;                                ;                                ;
;     -- normal mode                          ; 430                 ; 120                ; 567                            ; 0                              ;
;     -- arithmetic mode                      ; 386                 ; 8                  ; 85                             ; 0                              ;
;                                             ;                     ;                    ;                                ;                                ;
; Total registers                             ; 99                  ; 91                 ; 1419                           ; 0                              ;
;     -- Dedicated logic registers            ; 99 / 8064 ( 1 % )   ; 91 / 8064 ( 1 % )  ; 1419 / 8064 ( 18 % )           ; 0 / 8064 ( 0 % )               ;
;     -- I/O registers                        ; 0                   ; 0                  ; 0                              ; 0                              ;
;                                             ;                     ;                    ;                                ;                                ;
; Total LABs:  partially or completely used   ; 77 / 504 ( 15 % )   ; 13 / 504 ( 3 % )   ; 138 / 504 ( 27 % )             ; 0 / 504 ( 0 % )                ;
;                                             ;                     ;                    ;                                ;                                ;
; Virtual pins                                ; 0                   ; 0                  ; 0                              ; 0                              ;
; I/O pins                                    ; 44                  ; 0                  ; 0                              ; 0                              ;
; Embedded Multiplier 9-bit elements          ; 0 / 48 ( 0 % )      ; 0 / 48 ( 0 % )     ; 0 / 48 ( 0 % )                 ; 0 / 48 ( 0 % )                 ;
; Total memory bits                           ; 0                   ; 0                  ; 182272                         ; 0                              ;
; Total RAM block bits                        ; 0                   ; 0                  ; 211968                         ; 0                              ;
; JTAG                                        ; 1 / 1 ( 100 % )     ; 0 / 1 ( 0 % )      ; 0 / 1 ( 0 % )                  ; 0 / 1 ( 0 % )                  ;
; PLL                                         ; 0 / 1 ( 0 % )       ; 0 / 1 ( 0 % )      ; 0 / 1 ( 0 % )                  ; 1 / 1 ( 100 % )                ;
; M9K                                         ; 0 / 42 ( 0 % )      ; 0 / 42 ( 0 % )     ; 23 / 42 ( 54 % )               ; 0 / 42 ( 0 % )                 ;
; Clock control block                         ; 1 / 12 ( 8 % )      ; 0 / 12 ( 0 % )     ; 1 / 12 ( 8 % )                 ; 1 / 12 ( 8 % )                 ;
; User Flash Memory                           ; 1 / 1 ( 100 % )     ; 0 / 1 ( 0 % )      ; 0 / 1 ( 0 % )                  ; 0 / 1 ( 0 % )                  ;
; Analog-to-Digital Converter                 ; 1 / 1 ( 100 % )     ; 0 / 1 ( 0 % )      ; 0 / 1 ( 0 % )                  ; 0 / 1 ( 0 % )                  ;
;                                             ;                     ;                    ;                                ;                                ;
; Connections                                 ;                     ;                    ;                                ;                                ;
;     -- Input Connections                    ; 100                 ; 134                ; 1842                           ; 1                              ;
;     -- Registered Input Connections         ; 99                  ; 100                ; 1486                           ; 0                              ;
;     -- Output Connections                   ; 893                 ; 172                ; 34                             ; 978                            ;
;     -- Registered Output Connections        ; 72                  ; 172                ; 0                              ; 0                              ;
;                                             ;                     ;                    ;                                ;                                ;
; Internal Connections                        ;                     ;                    ;                                ;                                ;
;     -- Total Connections                    ; 3571                ; 888                ; 7509                           ; 985                            ;
;     -- Registered Connections               ; 869                 ; 628                ; 4278                           ; 0                              ;
;                                             ;                     ;                    ;                                ;                                ;
; External Connections                        ;                     ;                    ;                                ;                                ;
;     -- Top                                  ; 0                   ; 123                ; 770                            ; 100                            ;
;     -- sld_hub:auto_hub                     ; 123                 ; 20                 ; 163                            ; 0                              ;
;     -- sld_signaltap:auto_signaltap_0       ; 770                 ; 163                ; 64                             ; 879                            ;
;     -- hard_block:auto_generated_inst       ; 100                 ; 0                  ; 879                            ; 0                              ;
;                                             ;                     ;                    ;                                ;                                ;
; Partition Interface                         ;                     ;                    ;                                ;                                ;
;     -- Input Ports                          ; 4                   ; 45                 ; 336                            ; 1                              ;
;     -- Output Ports                         ; 133                 ; 62                 ; 193                            ; 1                              ;
;     -- Bidir Ports                          ; 0                   ; 0                  ; 0                              ; 0                              ;
;                                             ;                     ;                    ;                                ;                                ;
; Registered Ports                            ;                     ;                    ;                                ;                                ;
;     -- Registered Input Ports               ; 0                   ; 4                  ; 42                             ; 0                              ;
;     -- Registered Output Ports              ; 0                   ; 29                 ; 179                            ; 0                              ;
;                                             ;                     ;                    ;                                ;                                ;
; Port Connectivity                           ;                     ;                    ;                                ;                                ;
;     -- Input Ports driven by GND            ; 0                   ; 0                  ; 29                             ; 0                              ;
;     -- Output Ports driven by GND           ; 0                   ; 28                 ; 2                              ; 0                              ;
;     -- Input Ports driven by VCC            ; 0                   ; 0                  ; 19                             ; 0                              ;
;     -- Output Ports driven by VCC           ; 0                   ; 0                  ; 1                              ; 0                              ;
;     -- Input Ports with no Source           ; 0                   ; 25                 ; 93                             ; 0                              ;
;     -- Output Ports with no Source          ; 0                   ; 0                  ; 0                              ; 0                              ;
;     -- Input Ports with no Fanout           ; 0                   ; 30                 ; 107                            ; 0                              ;
;     -- Output Ports with no Fanout          ; 0                   ; 29                 ; 181                            ; 0                              ;
+---------------------------------------------+---------------------+--------------------+--------------------------------+--------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                                                  ;
+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
; Name       ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
; clk_in_16M ; K4    ; 2        ; 0            ; 6            ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ; 0         ;
+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name         ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; error_out    ; M9    ; 3        ; 15           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[0]  ; A9    ; 8        ; 6            ; 10           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[10] ; E15   ; 6        ; 31           ; 17           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[11] ; G11   ; 6        ; 31           ; 17           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[12] ; D11   ; 8        ; 17           ; 25           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[13] ; C8    ; 8        ; 15           ; 25           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[14] ; B13   ; 8        ; 15           ; 25           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[15] ; H13   ; 6        ; 31           ; 11           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[16] ; H12   ; 6        ; 31           ; 11           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[17] ; B8    ; 8        ; 15           ; 25           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; quotient[18] ; C15   ; 6        ; 31           ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[19] ; B6    ; 8        ; 6            ; 10           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; quotient[1]  ; E7    ; 8        ; 6            ; 10           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[20] ; A5    ; 8        ; 3            ; 10           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; quotient[2]  ; D7    ; 8        ; 6            ; 10           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[3]  ; D10   ; 8        ; 17           ; 25           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[4]  ; R14   ; 3        ; 13           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[5]  ; J11   ; 5        ; 31           ; 6            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[6]  ; K14   ; 5        ; 31           ; 6            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[7]  ; R13   ; 3        ; 19           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[8]  ; J15   ; 6        ; 31           ; 12           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; quotient[9]  ; A11   ; 8        ; 6            ; 10           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[0]     ; G5    ; 1A       ; 10           ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[10]    ; G7    ; 1B       ; 10           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[11]    ; G12   ; 6        ; 31           ; 17           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[12]    ; D2    ; 1A       ; 10           ; 22           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[13]    ; B12   ; 8        ; 11           ; 25           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[14]    ; F5    ; 1A       ; 10           ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[15]    ; G15   ; 6        ; 31           ; 12           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[16]    ; E2    ; 1A       ; 10           ; 19           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[17]    ; A7    ; 8        ; 3            ; 10           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[18]    ; P3    ; 3        ; 3            ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; test1[19]    ; R3    ; 3        ; 3            ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; test1[1]     ; B1    ; 1A       ; 10           ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[20]    ; R2    ; 2        ; 0            ; 5            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; test1[2]     ; G2    ; 1B       ; 10           ; 17           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[3]     ; H3    ; 1B       ; 10           ; 15           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[4]     ; E1    ; 1A       ; 10           ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[5]     ; J2    ; 1B       ; 10           ; 15           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[6]     ; E14   ; 6        ; 31           ; 17           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[7]     ; J12   ; 6        ; 31           ; 9            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[8]     ; P15   ; 3        ; 13           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; test1[9]     ; C1    ; 1A       ; 10           ; 20           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Dual Purpose and Dedicated Pins                                                                                                         ;
+----------+----------------------------------------------------+--------------------------------+---------------------+------------------+
; Location ; Pin Name                                           ; Reserved As                    ; User Signal Name    ; Pin Type         ;
+----------+----------------------------------------------------+--------------------------------+---------------------+------------------+
; G7       ; JTAGEN                                             ; Use as regular IO              ; test1[10]           ; Dual Purpose Pin ;
; G1       ; DIFFIO_RX_L11n, DIFFOUT_L11n, TMS, Low_Speed       ; Reserved as secondary function ; altera_reserved_tms ; Dual Purpose Pin ;
; J1       ; DIFFIO_RX_L11p, DIFFOUT_L11p, TCK, Low_Speed       ; Reserved as secondary function ; altera_reserved_tck ; Dual Purpose Pin ;
; H5       ; DIFFIO_RX_L12n, DIFFOUT_L12n, TDI, Low_Speed       ; Reserved as secondary function ; altera_reserved_tdi ; Dual Purpose Pin ;
; H4       ; DIFFIO_RX_L12p, DIFFOUT_L12p, TDO, Low_Speed       ; Reserved as secondary function ; altera_reserved_tdo ; Dual Purpose Pin ;
; B8       ; DIFFIO_RX_T16n, DIFFOUT_T16n, DEV_CLRn, Low_Speed  ; Use as regular IO              ; quotient[17]        ; Dual Purpose Pin ;
; D8       ; CONFIG_SEL, Low_Speed                              ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ;
; E8       ; nCONFIG, Low_Speed                                 ; Reserved as secondary function ; ~ALTERA_nCONFIG~    ; Dual Purpose Pin ;
; E7       ; DIFFIO_RX_T22n, DIFFOUT_T22n, CRC_ERROR, Low_Speed ; Use as regular IO              ; quotient[1]         ; Dual Purpose Pin ;
; D6       ; DIFFIO_RX_T24p, DIFFOUT_T24p, nSTATUS, Low_Speed   ; Reserved as secondary function ; ~ALTERA_nSTATUS~    ; Dual Purpose Pin ;
; E6       ; DIFFIO_RX_T24n, DIFFOUT_T24n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~  ; Dual Purpose Pin ;
+----------+----------------------------------------------------+--------------------------------+---------------------+------------------+


+------------------------------------------------------------+
; I/O Bank Usage                                             ;
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1A       ; 7 / 8 ( 88 % )   ; 2.5V          ; --           ;
; 1B       ; 8 / 10 ( 80 % )  ; 2.5V          ; --           ;
; 2        ; 2 / 10 ( 20 % )  ; 2.5V          ; --           ;
; 3        ; 6 / 28 ( 21 % )  ; 2.5V          ; --           ;
; 5        ; 2 / 12 ( 17 % )  ; 2.5V          ; --           ;
; 6        ; 10 / 16 ( 63 % ) ; 2.5V          ; --           ;
; 8        ; 17 / 28 ( 61 % ) ; 2.5V          ; --           ;
+----------+------------------+---------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                              ;
+----------+------------+----------+--------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                       ; Dir.   ; I/O Standard          ; Voltage   ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+--------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+
; A1       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; A2       ; 248        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; A3       ; 250        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; A5       ; 243        ; 8        ; quotient[20]                         ; output ; 2.5 V                 ;           ; Column I/O ; Y               ; no       ; Off          ;
; A7       ; 241        ; 8        ; test1[17]                            ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; A9       ; 237        ; 8        ; quotient[0]                          ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; A11      ; 239        ; 8        ; quotient[9]                          ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; A13      ; 231        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; --       ; --           ;
; A14      ; 227        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; A15      ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; B1       ; 10         ; 1A       ; test1[1]                             ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; B2       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; B3       ;            ; --       ; VCCA3                                ; power  ;                       ; 3.0V/3.3V ; --         ;                 ; --       ; --           ;
; B4       ; 245        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; B5       ;            ; 8        ; VCCIO8                               ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; B6       ; 238        ; 8        ; quotient[19]                         ; output ; 2.5 V                 ;           ; Column I/O ; Y               ; no       ; Off          ;
; B7       ; 236        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; B8       ; 226        ; 8        ; quotient[17]                         ; output ; 2.5 V                 ;           ; Column I/O ; Y               ; no       ; Off          ;
; B9       ;            ; 8        ; VCCIO8                               ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; B10      ;            ; 8        ; VCCIO8                               ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; B11      ; 235        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; B12      ; 233        ; 8        ; test1[13]                            ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; B13      ; 225        ; 8        ; quotient[14]                         ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; B14      ; 223        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; B15      ; 221        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; C1       ; 8          ; 1A       ; test1[9]                             ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; C2       ; 2          ; 1A       ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; C8       ; 224        ; 8        ; quotient[13]                         ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; C14      ; 179        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; C15      ; 177        ; 6        ; quotient[18]                         ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; D2       ; 0          ; 1A       ; test1[12]                            ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; D4       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; D5       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; D6       ; 244        ; 8        ; ~ALTERA_nSTATUS~ / RESERVED_INPUT    ; input  ; 2.5 V Schmitt Trigger ;           ; Column I/O ; N               ; no       ; Off          ;
; D7       ; 240        ; 8        ; quotient[2]                          ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; D8       ; 232        ; 8        ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input  ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; D9       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; D10      ; 222        ; 8        ; quotient[3]                          ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; D11      ; 220        ; 8        ; quotient[12]                         ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; D12      ; 190        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; D14      ;            ; --       ; VCCA2                                ; power  ;                       ; 3.0V/3.3V ; --         ;                 ; --       ; --           ;
; E1       ; 12         ; 1A       ; test1[4]                             ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; E2       ; 14         ; 1A       ; test1[16]                            ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; E4       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; E5       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; E6       ; 246        ; 8        ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT  ; input  ; 2.5 V Schmitt Trigger ;           ; Column I/O ; N               ; no       ; Off          ;
; E7       ; 242        ; 8        ; quotient[1]                          ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; E8       ; 234        ; 8        ; ~ALTERA_nCONFIG~ / RESERVED_INPUT    ; input  ; 2.5 V Schmitt Trigger ;           ; Column I/O ; N               ; no       ; Off          ;
; E9       ; 230        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; E10      ; 228        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; E11      ; 188        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; E12      ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; E14      ; 175        ; 6        ; test1[6]                             ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; E15      ; 173        ; 6        ; quotient[10]                         ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; F2       ;            ; 1A       ; VCCIO1A                              ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; F4       ;            ; --       ; VCCA3                                ; power  ;                       ; 3.0V/3.3V ; --         ;                 ; --       ; --           ;
; F5       ; 4          ; 1A       ; test1[14]                            ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; F11      ; 176        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; F12      ; 178        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; F14      ;            ; 6        ; VCCIO6                               ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; G1       ; 20         ; 1B       ; altera_reserved_tms                  ; input  ; 2.5 V Schmitt Trigger ;           ; Row I/O    ; N               ; no       ; Off          ;
; G2       ; 21         ; 1B       ; test1[2]                             ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; G4       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; G5       ; 6          ; 1A       ; test1[0]                             ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; G7       ; 18         ; 1B       ; test1[10]                            ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; G8       ;            ; --       ; VCC_ONE                              ; power  ;                       ; 3.0V/3.3V ; --         ;                 ; --       ; --           ;
; G9       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; G11      ; 172        ; 6        ; quotient[11]                         ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; G12      ; 174        ; 6        ; test1[11]                            ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; G14      ;            ; 6        ; VCCIO6                               ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; G15      ; 158        ; 6        ; test1[15]                            ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; H2       ;            ; 1B       ; VCCIO1B                              ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; H3       ; 28         ; 1B       ; test1[3]                             ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; H4       ; 26         ; 1B       ; altera_reserved_tdo                  ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; H5       ; 24         ; 1B       ; altera_reserved_tdi                  ; input  ; 2.5 V Schmitt Trigger ;           ; Row I/O    ; N               ; no       ; Off          ;
; H7       ;            ; --       ; VCC_ONE                              ; power  ;                       ; 3.0V/3.3V ; --         ;                 ; --       ; --           ;
; H8       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; H9       ;            ; --       ; VCC_ONE                              ; power  ;                       ; 3.0V/3.3V ; --         ;                 ; --       ; --           ;
; H11      ; 150        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; H12      ; 152        ; 6        ; quotient[16]                         ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; H13      ; 154        ; 6        ; quotient[15]                         ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; H14      ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; J1       ; 22         ; 1B       ; altera_reserved_tck                  ; input  ; 2.5 V Schmitt Trigger ;           ; Row I/O    ; N               ; no       ; Off          ;
; J2       ; 30         ; 1B       ; test1[5]                             ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; J4       ; 36         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; J5       ; 38         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; J7       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; J8       ;            ; --       ; VCC_ONE                              ; power  ;                       ; 3.0V/3.3V ; --         ;                 ; --       ; --           ;
; J9       ; 140        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; J11      ; 142        ; 5        ; quotient[5]                          ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; J12      ; 148        ; 6        ; test1[7]                             ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; J14      ; 143        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; J15      ; 156        ; 6        ; quotient[8]                          ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; K2       ; 34         ; 1B       ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; K4       ; 42         ; 2        ; clk_in_16M                           ; input  ; 3.3-V LVCMOS          ;           ; Row I/O    ; Y               ; no       ; Off          ;
; K5       ; 40         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; K11      ; 132        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; K12      ; 134        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; K14      ; 141        ; 5        ; quotient[6]                          ; output ; 2.5 V                 ;           ; Row I/O    ; N               ; no       ; Off          ;
; L1       ; 32         ; 1B       ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; L2       ;            ; 2        ; VCCIO2                               ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; L4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; L5       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; L6       ; 64         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; L7       ; 66         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; L8       ; 72         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; L9       ; 84         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; L10      ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; L11      ; 122        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; L12      ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; L14      ;            ; 5        ; VCCIO5                               ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; L15      ; 135        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; --       ; --           ;
; M2       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; M4       ; 60         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; M5       ; 62         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; M6       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; M7       ; 74         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; M8       ; 76         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; M9       ; 86         ; 3        ; error_out                            ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; M10      ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; M11      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; M12      ; 120        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; M14      ; 133        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; N1       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; N2       ;            ; --       ; VCCA1                                ; power  ;                       ; 3.0V/3.3V ; --         ;                 ; --       ; --           ;
; N8       ; 78         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; N14      ; 123        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; N15      ; 121        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; P1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; --       ; --           ;
; P2       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Row I/O    ;                 ; no       ; On           ;
; P3       ; 61         ; 3        ; test1[18]                            ; output ; 2.5 V                 ;           ; Column I/O ; Y               ; no       ; Off          ;
; P4       ; 65         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; P5       ;            ; 3        ; VCCIO3                               ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; P6       ; 68         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; P7       ; 70         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; P8       ; 71         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; P9       ; 73         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; P10      ;            ; 3        ; VCCIO3                               ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; P11      ;            ; 3        ; VCCIO3                               ; power  ;                       ; 2.5V      ; --         ;                 ; --       ; --           ;
; P12      ; 79         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; P13      ;            ; --       ; VCCA4                                ; power  ;                       ; 3.0V/3.3V ; --         ;                 ; --       ; --           ;
; P14      ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; P15      ; 82         ; 3        ; test1[8]                             ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; R1       ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
; R2       ; 47         ; 2        ; test1[20]                            ; output ; 2.5 V                 ;           ; Row I/O    ; Y               ; no       ; Off          ;
; R3       ; 63         ; 3        ; test1[19]                            ; output ; 2.5 V                 ;           ; Column I/O ; Y               ; no       ; Off          ;
; R5       ; 67         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; R7       ; 69         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; R9       ; 75         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; no       ; On           ;
; R11      ; 77         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP      ;        ;                       ;           ; Column I/O ;                 ; --       ; --           ;
; R13      ; 94         ; 3        ; quotient[7]                          ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; R14      ; 80         ; 3        ; quotient[4]                          ; output ; 2.5 V                 ;           ; Column I/O ; N               ; no       ; Off          ;
; R15      ;            ;          ; GND                                  ; gnd    ;                       ;           ; --         ;                 ; --       ; --           ;
+----------+------------+----------+--------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.


+----------------------------------------------------------------------------------------------------------------------------------+
; PLL Summary                                                                                                                      ;
+-------------------------------+--------------------------------------------------------------------------------------------------+
; Name                          ; alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated|pll1 ;
+-------------------------------+--------------------------------------------------------------------------------------------------+
; SDC pin name                  ; a_pll_220_110|altpll_component|auto_generated|pll1                                               ;
; PLL mode                      ; Normal                                                                                           ;
; Compensate clock              ; clock0                                                                                           ;
; Compensated input/output pins ; --                                                                                               ;
; Switchover type               ; --                                                                                               ;
; Input frequency 0             ; 16.0 MHz                                                                                         ;
; Input frequency 1             ; --                                                                                               ;
; Nominal PFD frequency         ; 16.0 MHz                                                                                         ;
; Nominal VCO frequency         ; 576.0 MHz                                                                                        ;
; VCO post scale K counter      ; 2                                                                                                ;
; VCO frequency control         ; Auto                                                                                             ;
; VCO phase shift step          ; 217 ps                                                                                           ;
; VCO multiply                  ; --                                                                                               ;
; VCO divide                    ; --                                                                                               ;
; Freq min lock                 ; 9.8 MHz                                                                                          ;
; Freq max lock                 ; 18.06 MHz                                                                                        ;
; M VCO Tap                     ; 0                                                                                                ;
; M Initial                     ; 1                                                                                                ;
; M value                       ; 36                                                                                               ;
; N value                       ; 1                                                                                                ;
; Charge pump current           ; setting 1                                                                                        ;
; Loop filter resistance        ; setting 24                                                                                       ;
; Loop filter capacitance       ; setting 0                                                                                        ;
; Bandwidth                     ; 450 kHz to 980 kHz                                                                               ;
; Bandwidth type                ; Medium                                                                                           ;
; Real time reconfigurable      ; Off                                                                                              ;
; Scan chain MIF file           ; --                                                                                               ;
; Preserve PLL counter order    ; Off                                                                                              ;
; PLL location                  ; PLL_1                                                                                            ;
; Inclk0 signal                 ; clk_in_16M                                                                                       ;
; Inclk1 signal                 ; --                                                                                               ;
; Inclk0 signal type            ; Dedicated Pin                                                                                    ;
; Inclk1 signal type            ; --                                                                                               ;
+-------------------------------+--------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Usage                                                                                                                                                                                                                                                                                                                                        ;
+--------------------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------------+
; Name                                                                                                         ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                              ;
+--------------------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------------+
; alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated|wire_pll1_clk[0] ; clock0       ; 6    ; 1   ; 96.0 MHz         ; 0 (0 ps)    ; 7.50 (217 ps)    ; 50/50      ; C0      ; 6             ; 3/3 Even   ; --            ; 1       ; 0       ; a_pll_220_110|altpll_component|auto_generated|pll1|clk[0] ;
+--------------------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------------+


+----------------------------------------------+
; I/O Assignment Warnings                      ;
+--------------+-------------------------------+
; Pin Name     ; Reason                        ;
+--------------+-------------------------------+
; error_out    ; Incomplete set of assignments ;
; quotient[20] ; Incomplete set of assignments ;
; quotient[19] ; Incomplete set of assignments ;
; quotient[18] ; Incomplete set of assignments ;
; quotient[17] ; Incomplete set of assignments ;
; quotient[16] ; Incomplete set of assignments ;
; quotient[15] ; Incomplete set of assignments ;
; quotient[14] ; Incomplete set of assignments ;
; quotient[13] ; Incomplete set of assignments ;
; quotient[12] ; Incomplete set of assignments ;
; quotient[11] ; Incomplete set of assignments ;
; quotient[10] ; Incomplete set of assignments ;
; quotient[9]  ; Incomplete set of assignments ;
; quotient[8]  ; Incomplete set of assignments ;
; quotient[7]  ; Incomplete set of assignments ;
; quotient[6]  ; Incomplete set of assignments ;
; quotient[5]  ; Incomplete set of assignments ;
; quotient[4]  ; Incomplete set of assignments ;
; quotient[3]  ; Incomplete set of assignments ;
; quotient[2]  ; Incomplete set of assignments ;
; quotient[1]  ; Incomplete set of assignments ;
; quotient[0]  ; Incomplete set of assignments ;
; test1[20]    ; Incomplete set of assignments ;
; test1[19]    ; Incomplete set of assignments ;
; test1[18]    ; Incomplete set of assignments ;
; test1[17]    ; Incomplete set of assignments ;
; test1[16]    ; Incomplete set of assignments ;
; test1[15]    ; Incomplete set of assignments ;
; test1[14]    ; Incomplete set of assignments ;
; test1[13]    ; Incomplete set of assignments ;
; test1[12]    ; Incomplete set of assignments ;
; test1[11]    ; Incomplete set of assignments ;
; test1[10]    ; Incomplete set of assignments ;
; test1[9]     ; Incomplete set of assignments ;
; test1[8]     ; Incomplete set of assignments ;
; test1[7]     ; Incomplete set of assignments ;
; test1[6]     ; Incomplete set of assignments ;
; test1[5]     ; Incomplete set of assignments ;
; test1[4]     ; Incomplete set of assignments ;
; test1[3]     ; Incomplete set of assignments ;
; test1[2]     ; Incomplete set of assignments ;
; test1[1]     ; Incomplete set of assignments ;
; test1[0]     ; Incomplete set of assignments ;
; error_out    ; Missing location assignment   ;
; quotient[18] ; Missing location assignment   ;
; quotient[16] ; Missing location assignment   ;
; quotient[15] ; Missing location assignment   ;
; quotient[14] ; Missing location assignment   ;
; quotient[13] ; Missing location assignment   ;
; quotient[12] ; Missing location assignment   ;
; quotient[11] ; Missing location assignment   ;
; quotient[10] ; Missing location assignment   ;
; quotient[9]  ; Missing location assignment   ;
; quotient[8]  ; Missing location assignment   ;
; quotient[7]  ; Missing location assignment   ;
; quotient[6]  ; Missing location assignment   ;
; quotient[5]  ; Missing location assignment   ;
; quotient[4]  ; Missing location assignment   ;
; quotient[3]  ; Missing location assignment   ;
; quotient[2]  ; Missing location assignment   ;
; quotient[1]  ; Missing location assignment   ;
; quotient[0]  ; Missing location assignment   ;
; test1[17]    ; Missing location assignment   ;
; test1[16]    ; Missing location assignment   ;
; test1[15]    ; Missing location assignment   ;
; test1[14]    ; Missing location assignment   ;
; test1[13]    ; Missing location assignment   ;
; test1[12]    ; Missing location assignment   ;
; test1[11]    ; Missing location assignment   ;
; test1[10]    ; Missing location assignment   ;
; test1[9]     ; Missing location assignment   ;
; test1[8]     ; Missing location assignment   ;
; test1[7]     ; Missing location assignment   ;
; test1[6]     ; Missing location assignment   ;
; test1[5]     ; Missing location assignment   ;
; test1[4]     ; Missing location assignment   ;
; test1[3]     ; Missing location assignment   ;
; test1[2]     ; Missing location assignment   ;
; test1[1]     ; Missing location assignment   ;
; test1[0]     ; Missing location assignment   ;
+--------------+-------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
; Compilation Hierarchy Node                                                                                                              ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name                                                                                                                                                                                                                                                                                                                                 ; Entity Name                       ; Library Name ;
+-----------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
; |fs20_01                                                                                                                                ; 2546 (3)    ; 1609 (0)                  ; 0 (0)         ; 182272      ; 23   ; 1          ; 0            ; 0       ; 0         ; 44   ; 0            ; 937 (3)      ; 950 (0)           ; 659 (0)          ; 0          ; |fs20_01                                                                                                                                                                                                                                                                                                                                            ; fs20_01                           ; work         ;
;    |alt_pll_220_110:a_pll_220_110|                                                                                                      ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0          ; |fs20_01|alt_pll_220_110:a_pll_220_110                                                                                                                                                                                                                                                                                                              ; alt_pll_220_110                   ; work         ;
;       |altpll:altpll_component|                                                                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0          ; |fs20_01|alt_pll_220_110:a_pll_220_110|altpll:altpll_component                                                                                                                                                                                                                                                                                      ; altpll                            ; work         ;
;          |alt_pll_220_110_altpll:auto_generated|                                                                                        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0          ; |fs20_01|alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated                                                                                                                                                                                                                                                ; alt_pll_220_110_altpll            ; work         ;
;    |div_no_pipeline:no_pipeline|                                                                                                        ; 401 (0)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 386 (0)      ; 0 (0)             ; 15 (0)           ; 0          ; |fs20_01|div_no_pipeline:no_pipeline                                                                                                                                                                                                                                                                                                                ; div_no_pipeline                   ; work         ;
;       |lpm_divide:LPM_DIVIDE_component|                                                                                                 ; 401 (0)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 386 (0)      ; 0 (0)             ; 15 (0)           ; 0          ; |fs20_01|div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component                                                                                                                                                                                                                                                                                ; lpm_divide                        ; work         ;
;          |lpm_divide_p0r:auto_generated|                                                                                                ; 401 (0)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 386 (0)      ; 0 (0)             ; 15 (0)           ; 0          ; |fs20_01|div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated                                                                                                                                                                                                                                                  ; lpm_divide_p0r                    ; work         ;
;             |sign_div_unsign_6nh:divider|                                                                                               ; 401 (0)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 386 (0)      ; 0 (0)             ; 15 (0)           ; 0          ; |fs20_01|div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider                                                                                                                                                                                                                      ; sign_div_unsign_6nh               ; work         ;
;                |alt_u_div_lke:divider|                                                                                                  ; 401 (401)   ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 386 (386)    ; 0 (0)             ; 15 (15)          ; 0          ; |fs20_01|div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider                                                                                                                                                                                                ; alt_u_div_lke                     ; work         ;
;    |inc_div_test:inst1|                                                                                                                 ; 372 (0)     ; 56 (0)                    ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 316 (0)      ; 3 (0)             ; 53 (0)           ; 0          ; |fs20_01|inc_div_test:inst1                                                                                                                                                                                                                                                                                                                         ; inc_div_test                      ; work         ;
;       |lpm_divide:LPM_DIVIDE_component|                                                                                                 ; 372 (0)     ; 56 (0)                    ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 316 (0)      ; 3 (0)             ; 53 (0)           ; 0          ; |fs20_01|inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component                                                                                                                                                                                                                                                                                         ; lpm_divide                        ; work         ;
;          |lpm_divide_uft:auto_generated|                                                                                                ; 372 (0)     ; 56 (0)                    ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 316 (0)      ; 3 (0)             ; 53 (0)           ; 0          ; |fs20_01|inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated                                                                                                                                                                                                                                                           ; lpm_divide_uft                    ; work         ;
;             |sign_div_unsign_0qi:divider|                                                                                               ; 372 (0)     ; 56 (0)                    ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 316 (0)      ; 3 (0)             ; 53 (0)           ; 0          ; |fs20_01|inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider                                                                                                                                                                                                                               ; sign_div_unsign_0qi               ; work         ;
;                |alt_u_div_eqf:divider|                                                                                                  ; 372 (372)   ; 56 (56)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 316 (316)    ; 3 (3)             ; 53 (53)          ; 0          ; |fs20_01|inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider                                                                                                                                                                                                         ; alt_u_div_eqf                     ; work         ;
;    |sld_hub:auto_hub|                                                                                                                   ; 154 (1)     ; 91 (0)                    ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 63 (1)       ; 26 (0)            ; 65 (0)           ; 0          ; |fs20_01|sld_hub:auto_hub                                                                                                                                                                                                                                                                                                                           ; sld_hub                           ; altera_sld   ;
;       |alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric| ; 153 (0)     ; 91 (0)                    ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 62 (0)       ; 26 (0)            ; 65 (0)           ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric                                                                                                                                                                                           ; alt_sld_fab_with_jtag_input       ; altera_sld   ;
;          |alt_sld_fab:instrumentation_fabric|                                                                                           ; 153 (0)     ; 91 (0)                    ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 62 (0)       ; 26 (0)            ; 65 (0)           ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric                                                                                                                                                        ; alt_sld_fab                       ; alt_sld_fab  ;
;             |alt_sld_fab_alt_sld_fab:alt_sld_fab|                                                                                       ; 153 (6)     ; 91 (5)                    ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 62 (1)       ; 26 (4)            ; 65 (0)           ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab                                                                                                                    ; alt_sld_fab_alt_sld_fab           ; alt_sld_fab  ;
;                |alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|                                                                            ; 148 (0)     ; 86 (0)                    ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 61 (0)       ; 22 (0)            ; 65 (0)           ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric                                                                        ; alt_sld_fab_alt_sld_fab_sldfabric ; alt_sld_fab  ;
;                   |sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|                                                                        ; 148 (106)   ; 86 (58)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 61 (47)      ; 22 (20)           ; 65 (40)          ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub                           ; sld_jtag_hub                      ; work         ;
;                      |sld_rom_sr:hub_info_reg|                                                                                          ; 21 (21)     ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 12 (12)      ; 0 (0)             ; 9 (9)            ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg   ; sld_rom_sr                        ; work         ;
;                      |sld_shadow_jsm:shadow_jsm|                                                                                        ; 21 (21)     ; 19 (19)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 2 (2)             ; 17 (17)          ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm ; sld_shadow_jsm                    ; altera_sld   ;
;    |sld_signaltap:auto_signaltap_0|                                                                                                     ; 1566 (179)  ; 1419 (178)                ; 0 (0)         ; 182272      ; 23   ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 147 (2)      ; 914 (177)         ; 505 (0)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                                                                                                             ; sld_signaltap                     ; work         ;
;       |sld_signaltap_impl:sld_signaltap_body|                                                                                           ; 1387 (0)    ; 1241 (0)                  ; 0 (0)         ; 182272      ; 23   ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 145 (0)      ; 737 (0)           ; 505 (0)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body                                                                                                                                                                                                                                                                       ; sld_signaltap_impl                ; work         ;
;          |sld_signaltap_implb:sld_signaltap_body|                                                                                       ; 1387 (468)  ; 1241 (438)                ; 0 (0)         ; 182272      ; 23   ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 145 (34)     ; 737 (379)         ; 505 (55)         ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body                                                                                                                                                                                                                                ; sld_signaltap_implb               ; work         ;
;             |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|                                                            ; 72 (70)     ; 70 (70)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 47 (47)           ; 24 (0)           ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem                                                                                                                                                                 ; altdpram                          ; work         ;
;                |lpm_decode:wdecoder|                                                                                                    ; 2 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 1 (0)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder                                                                                                                                             ; lpm_decode                        ; work         ;
;                   |decode_3af:auto_generated|                                                                                           ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_3af:auto_generated                                                                                                                   ; decode_3af                        ; work         ;
;                |lpm_mux:mux|                                                                                                            ; 23 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 23 (0)           ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux                                                                                                                                                     ; lpm_mux                           ; work         ;
;                   |mux_h7c:auto_generated|                                                                                              ; 23 (23)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 23 (23)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_h7c:auto_generated                                                                                                                              ; mux_h7c                           ; work         ;
;             |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|                                                                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 182272      ; 23   ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram                                                                                                                                                                                ; altsyncram                        ; work         ;
;                |altsyncram_am14:auto_generated|                                                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 182272      ; 23   ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated                                                                                                                                                 ; altsyncram_am14                   ; work         ;
;             |lpm_shiftreg:segment_offset_config_deserialize|                                                                            ; 11 (11)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 11 (11)           ; 0 (0)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize                                                                                                                                                                                 ; lpm_shiftreg                      ; work         ;
;             |lpm_shiftreg:status_register|                                                                                              ; 17 (17)     ; 17 (17)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 17 (17)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:status_register                                                                                                                                                                                                   ; lpm_shiftreg                      ; work         ;
;             |serial_crc_16:\tdo_crc_gen:tdo_crc_calc|                                                                                   ; 14 (14)     ; 13 (13)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 13 (13)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc                                                                                                                                                                                        ; serial_crc_16                     ; work         ;
;             |sld_buffer_manager:sld_buffer_manager_inst|                                                                                ; 108 (108)   ; 64 (64)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 39 (39)      ; 19 (19)           ; 50 (50)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst                                                                                                                                                                                     ; sld_buffer_manager                ; work         ;
;             |sld_ela_control:ela_control|                                                                                               ; 491 (1)     ; 461 (1)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (0)       ; 281 (0)           ; 180 (1)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control                                                                                                                                                                                                    ; sld_ela_control                   ; work         ;
;                |lpm_shiftreg:trigger_config_deserialize|                                                                                ; 4 (4)       ; 4 (4)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 4 (4)             ; 0 (0)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize                                                                                                                                                            ; lpm_shiftreg                      ; work         ;
;                |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|                                 ; 445 (0)     ; 445 (0)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 267 (0)           ; 178 (0)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm                                                                                                             ; sld_ela_basic_multi_level_trigger ; work         ;
;                   |lpm_shiftreg:trigger_condition_deserialize|                                                                          ; 267 (267)   ; 267 (267)                 ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 267 (267)         ; 0 (0)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize                                                                  ; lpm_shiftreg                      ; work         ;
;                   |sld_mbpmg:\trigger_modules_gen:0:trigger_match|                                                                      ; 178 (0)     ; 178 (0)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 178 (0)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match                                                              ; sld_mbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|                                                            ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|                                                            ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|                                                            ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|                                                            ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|                                                            ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|                                                            ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|                                                            ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|                                                            ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:80:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:80:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:81:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:81:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:82:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:82:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:83:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:83:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:84:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:84:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:85:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:85:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:86:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:86:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:87:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:87:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:88:sm1|                                                           ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:88:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|                                                            ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|                                                            ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1        ; sld_sbpmg                         ; work         ;
;                |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|                                                          ; 41 (31)     ; 11 (1)                    ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (30)      ; 10 (0)            ; 1 (1)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity                                                                                                                                      ; sld_ela_trigger_flow_mgr          ; work         ;
;                   |lpm_shiftreg:trigger_config_deserialize|                                                                             ; 10 (10)     ; 10 (10)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 10 (10)           ; 0 (0)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize                                                                                              ; lpm_shiftreg                      ; work         ;
;             |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|                                          ; 177 (12)    ; 159 (0)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 18 (12)      ; 0 (0)             ; 159 (0)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst                                                                                                                                               ; sld_offload_buffer_mgr            ; work         ;
;                |lpm_counter:\adv_point_3_and_more:advance_pointer_counter|                                                              ; 9 (0)       ; 7 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 7 (0)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter                                                                                     ; lpm_counter                       ; work         ;
;                   |cntr_lrh:auto_generated|                                                                                             ; 9 (9)       ; 7 (7)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 7 (7)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_lrh:auto_generated                                                             ; cntr_lrh                          ; work         ;
;                |lpm_counter:read_pointer_counter|                                                                                       ; 11 (0)      ; 11 (0)                    ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 11 (0)           ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter                                                                                                              ; lpm_counter                       ; work         ;
;                   |cntr_6ki:auto_generated|                                                                                             ; 11 (11)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 11 (11)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_6ki:auto_generated                                                                                      ; cntr_6ki                          ; work         ;
;                |lpm_counter:status_advance_pointer_counter|                                                                             ; 7 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 5 (0)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter                                                                                                    ; lpm_counter                       ; work         ;
;                   |cntr_4rh:auto_generated|                                                                                             ; 7 (7)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 5 (5)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_4rh:auto_generated                                                                            ; cntr_4rh                          ; work         ;
;                |lpm_counter:status_read_pointer_counter|                                                                                ; 3 (0)       ; 1 (0)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 1 (0)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter                                                                                                       ; lpm_counter                       ; work         ;
;                   |cntr_odi:auto_generated|                                                                                             ; 3 (3)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 1 (1)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_odi:auto_generated                                                                               ; cntr_odi                          ; work         ;
;                |lpm_shiftreg:info_data_shift_out|                                                                                       ; 23 (23)     ; 23 (23)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 23 (23)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out                                                                                                              ; lpm_shiftreg                      ; work         ;
;                |lpm_shiftreg:ram_data_shift_out|                                                                                        ; 89 (89)     ; 89 (89)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 89 (89)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out                                                                                                               ; lpm_shiftreg                      ; work         ;
;                |lpm_shiftreg:status_data_shift_out|                                                                                     ; 23 (23)     ; 23 (23)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 23 (23)          ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out                                                                                                            ; lpm_shiftreg                      ; work         ;
;             |sld_rom_sr:crc_rom_sr|                                                                                                     ; 30 (30)     ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 22 (22)      ; 0 (0)             ; 8 (8)            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr                                                                                                                                                                                                          ; sld_rom_sr                        ; work         ;
;    |test_div_1:inst|                                                                                                                    ; 65 (65)     ; 43 (43)                   ; 0 (0)         ; 0           ; 0    ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 22 (22)      ; 7 (7)             ; 36 (36)          ; 0          ; |fs20_01|test_div_1:inst                                                                                                                                                                                                                                                                                                                            ; test_div_1                        ; work         ;
+-----------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------+
; Delay Chain Summary                                                                          ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+
; Name         ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+
; error_out    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[20] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[19] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[18] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[17] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[16] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[15] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[14] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[13] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[12] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[11] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[10] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[9]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[8]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[7]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[6]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[5]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[4]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[3]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[2]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[1]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; quotient[0]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[20]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[19]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[18]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[17]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[16]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[15]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[14]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[13]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[12]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[11]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[10]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[9]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[8]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[7]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[6]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[5]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[4]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[3]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[2]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[1]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; test1[0]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; clk_in_16M   ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+


+---------------------------------------------------+
; Pad To Core Delay Chain Fanout                    ;
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; clk_in_16M          ;                   ;         ;
+---------------------+-------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
; Name                                                                                                                                                                                                                                                                                                                                                        ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
; alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated|wire_pll1_clk[0]                                                                                                                                                                                                                                                ; PLL_1              ; 978     ; Clock                      ; yes    ; Global Clock         ; GCLK3            ; --                        ;
; altera_internal_jtag~TCKUTAP                                                                                                                                                                                                                                                                                                                                ; JTAG_X10_Y11_N0    ; 677     ; Clock                      ; yes    ; Global Clock         ; GCLK1            ; --                        ;
; altera_internal_jtag~TMSUTAP                                                                                                                                                                                                                                                                                                                                ; JTAG_X10_Y11_N0    ; 23      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; clk_in_16M                                                                                                                                                                                                                                                                                                                                                  ; PIN_K4             ; 1       ; Clock                      ; no     ; --                   ; --               ; --                        ;
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_15_result_int[13]~26                                                                                                                                                                                             ; LCCOMB_X22_Y11_N26 ; 13      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|clr_reg                                    ; FF_X11_Y6_N21      ; 27      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|design_hash_proc~0                         ; LCCOMB_X6_Y9_N20   ; 4       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|hub_info_reg_ena                           ; LCCOMB_X10_Y8_N14  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|hub_info_reg_ena~0                         ; LCCOMB_X11_Y8_N16  ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|identity_contrib_shift_reg[0]~1            ; LCCOMB_X10_Y8_N0   ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][0]~0                            ; LCCOMB_X12_Y7_N30  ; 10      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][4]                              ; FF_X12_Y6_N31      ; 29      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][7]                              ; FF_X12_Y6_N25      ; 29      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[2]~2                              ; LCCOMB_X11_Y6_N14  ; 9       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[4]~7               ; LCCOMB_X2_Y9_N2    ; 5       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[4]~8               ; LCCOMB_X9_Y9_N2    ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|reset_ena_reg_proc~0                       ; LCCOMB_X11_Y7_N14  ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|WORD_SR[1]~17      ; LCCOMB_X10_Y7_N14  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[0]~13 ; LCCOMB_X9_Y7_N28   ; 5       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[0]~20 ; LCCOMB_X10_Y7_N28  ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[0]         ; FF_X11_Y6_N27      ; 15      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[11]        ; FF_X9_Y9_N7        ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[3]         ; FF_X9_Y9_N23       ; 36      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[4]         ; FF_X11_Y8_N13      ; 32      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|virtual_ir_dr_scan_proc~0                  ; LCCOMB_X9_Y9_N28   ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|virtual_ir_scan_reg                        ; FF_X9_Y9_N19       ; 34      ; Async. clear, Clock enable ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|sldfabric_ident_writedata[0]~0                                                                                                      ; LCCOMB_X10_Y8_N22  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_3af:auto_generated|eq_node[0]~1                                                                                                                       ; LCCOMB_X16_Y6_N8   ; 23      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_3af:auto_generated|eq_node[1]~0                                                                                                                       ; LCCOMB_X16_Y6_N10  ; 23      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_enable_delayed                                                                                                                                                                                                                     ; FF_X16_Y6_N23      ; 26      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|collect_data                                                                                                                                                                                                                                    ; LCCOMB_X16_Y6_N26  ; 29      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|process_0~0                                                                                                                                                                                                                                     ; LCCOMB_X16_Y7_N16  ; 32      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|process_0~1                                                                                                                                                                                                                                     ; LCCOMB_X16_Y7_N2   ; 32      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all                                                                                                                                                                                                                                       ; FF_X12_Y5_N1       ; 483     ; Async. clear               ; yes    ; Global Clock         ; GCLK4            ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[10]~1                                                                                                                                                                                              ; LCCOMB_X18_Y7_N16  ; 13      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|final_trigger_set~4                                                                                                                                                                                  ; LCCOMB_X16_Y6_N14  ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]~0                                                                                                                                                                   ; LCCOMB_X16_Y6_N16  ; 11      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|Equal2~1                                                                                                                                                       ; LCCOMB_X14_Y5_N20  ; 1       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset                                                                                                                                             ; LCCOMB_X12_Y5_N30  ; 11      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_lrh:auto_generated|counter_reg_bit[6]~0                                                         ; LCCOMB_X13_Y5_N2   ; 7       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_4rh:auto_generated|counter_reg_bit[4]~0                                                                        ; LCCOMB_X14_Y5_N24  ; 5       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_odi:auto_generated|counter_reg_bit[0]~0                                                                           ; LCCOMB_X12_Y5_N24  ; 1       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter_clk_ena                                                                                                                                   ; LCCOMB_X12_Y5_N16  ; 11      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[1]~8                                                                                                                                                                                                              ; LCCOMB_X9_Y6_N18   ; 4       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[1]~9                                                                                                                                                                                                              ; LCCOMB_X9_Y6_N4    ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[2]~5                                                                                                                                                                                                         ; LCCOMB_X9_Y6_N20   ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|status_shift_enable~1                                                                                                                                                                                                                           ; LCCOMB_X14_Y6_N6   ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[14]~34                                                                                                                                                                                                                          ; LCCOMB_X18_Y7_N14  ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[0]~1                                                                                                                                                                                                                      ; LCCOMB_X17_Y7_N16  ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|trigger_setup_ena                                                                                                                                                                                                                               ; LCCOMB_X16_Y7_N10  ; 292     ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; test_div_1:inst|S_counter_reg[0]~11                                                                                                                                                                                                                                                                                                                         ; LCCOMB_X16_Y11_N30 ; 5       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; test_div_1:inst|S_divider_clk_en_reg                                                                                                                                                                                                                                                                                                                        ; FF_X16_Y11_N3      ; 59      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; test_div_1:inst|S_quotient_bak_reg[10]~1                                                                                                                                                                                                                                                                                                                    ; LCCOMB_X16_Y11_N16 ; 11      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; test_div_1:inst|S_state_reg.idle                                                                                                                                                                                                                                                                                                                            ; FF_X16_Y11_N11     ; 27      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; test_div_1:inst|WideNor0                                                                                                                                                                                                                                                                                                                                    ; LCCOMB_X16_Y11_N14 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                                                                                                                                                                                    ;
+-----------------------------------------------------------------------------------------------------------------------+-----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; Name                                                                                                                  ; Location        ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-----------------------------------------------------------------------------------------------------------------------+-----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated|wire_pll1_clk[0]          ; PLL_1           ; 978     ; 36                                   ; Global Clock         ; GCLK3            ; --                        ;
; altera_internal_jtag~TCKUTAP                                                                                          ; JTAG_X10_Y11_N0 ; 677     ; 0                                    ; Global Clock         ; GCLK1            ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all ; FF_X12_Y5_N1    ; 483     ; 0                                    ; Global Clock         ; GCLK4            ; --                        ;
+-----------------------------------------------------------------------------------------------------------------------+-----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+------------------------+------------------------+----------+------------------------+---------------+
; Name                                                                                                                                                                                                  ; Type ; Mode             ; Clock Mode  ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size   ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                                                                                                                                                                                                                                                                 ; Mixed Width RDW Mode ; Port A RDW Mode        ; Port B RDW Mode        ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+------------------------+------------------------+----------+------------------------+---------------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 2048         ; 89           ; 2048         ; 89           ; yes                    ; no                      ; yes                    ; no                      ; 182272 ; 2048                        ; 89                          ; 2048                        ; 89                          ; 182272              ; 23   ; None ; M9K_X5_Y3_N0, M9K_X5_Y6_N0, M9K_X8_Y2_N0, M9K_X8_Y6_N0, M9K_X26_Y4_N0, M9K_X26_Y7_N0, M9K_X26_Y6_N0, M9K_X26_Y3_N0, M9K_X26_Y2_N0, M9K_X26_Y8_N0, M9K_X26_Y9_N0, M9K_X26_Y5_N0, M9K_X5_Y7_N0, M9K_X5_Y9_N0, M9K_X8_Y7_N0, M9K_X8_Y8_N0, M9K_X8_Y9_N0, M9K_X5_Y8_N0, M9K_X8_Y4_N0, M9K_X8_Y5_N0, M9K_X8_Y3_N0, M9K_X5_Y4_N0, M9K_X5_Y5_N0 ; Don't care           ; New data with NBE Read ; New data with NBE Read ; Off      ; No                     ; No - Unknown  ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+------------------------+------------------------+----------+------------------------+---------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.


+-------------------------------------------------+
; Routing Usage Summary                           ;
+-----------------------+-------------------------+
; Routing Resource Type ; Usage                   ;
+-----------------------+-------------------------+
; Block interconnects   ; 2,868 / 27,275 ( 11 % ) ;
; C16 interconnects     ; 17 / 1,240 ( 1 % )      ;
; C4 interconnects      ; 1,185 / 20,832 ( 6 % )  ;
; Direct links          ; 722 / 27,275 ( 3 % )    ;
; Global clocks         ; 3 / 10 ( 30 % )         ;
; Local interconnects   ; 1,556 / 8,064 ( 19 % )  ;
; R24 interconnects     ; 30 / 1,320 ( 2 % )      ;
; R4 interconnects      ; 1,414 / 28,560 ( 5 % )  ;
+-----------------------+-------------------------+


+-----------------------------------------------------------------------------+
; LAB Logic Elements                                                          ;
+---------------------------------------------+-------------------------------+
; Number of Logic Elements  (Average = 12.54) ; Number of LABs  (Total = 203) ;
+---------------------------------------------+-------------------------------+
; 1                                           ; 11                            ;
; 2                                           ; 4                             ;
; 3                                           ; 2                             ;
; 4                                           ; 2                             ;
; 5                                           ; 5                             ;
; 6                                           ; 2                             ;
; 7                                           ; 1                             ;
; 8                                           ; 2                             ;
; 9                                           ; 5                             ;
; 10                                          ; 9                             ;
; 11                                          ; 15                            ;
; 12                                          ; 15                            ;
; 13                                          ; 16                            ;
; 14                                          ; 18                            ;
; 15                                          ; 23                            ;
; 16                                          ; 73                            ;
+---------------------------------------------+-------------------------------+


+--------------------------------------------------------------------+
; LAB-wide Signals                                                   ;
+------------------------------------+-------------------------------+
; LAB-wide Signals  (Average = 1.79) ; Number of LABs  (Total = 203) ;
+------------------------------------+-------------------------------+
; 1 Async. clear                     ; 75                            ;
; 1 Clock                            ; 122                           ;
; 1 Clock enable                     ; 97                            ;
; 1 Sync. clear                      ; 2                             ;
; 1 Sync. load                       ; 6                             ;
; 2 Clock enables                    ; 10                            ;
; 2 Clocks                           ; 52                            ;
+------------------------------------+-------------------------------+


+------------------------------------------------------------------------------+
; LAB Signals Sourced                                                          ;
+----------------------------------------------+-------------------------------+
; Number of Signals Sourced  (Average = 19.18) ; Number of LABs  (Total = 203) ;
+----------------------------------------------+-------------------------------+
; 0                                            ; 0                             ;
; 1                                            ; 5                             ;
; 2                                            ; 7                             ;
; 3                                            ; 3                             ;
; 4                                            ; 2                             ;
; 5                                            ; 3                             ;
; 6                                            ; 0                             ;
; 7                                            ; 1                             ;
; 8                                            ; 0                             ;
; 9                                            ; 3                             ;
; 10                                           ; 4                             ;
; 11                                           ; 3                             ;
; 12                                           ; 4                             ;
; 13                                           ; 2                             ;
; 14                                           ; 1                             ;
; 15                                           ; 9                             ;
; 16                                           ; 22                            ;
; 17                                           ; 14                            ;
; 18                                           ; 7                             ;
; 19                                           ; 5                             ;
; 20                                           ; 9                             ;
; 21                                           ; 10                            ;
; 22                                           ; 15                            ;
; 23                                           ; 13                            ;
; 24                                           ; 12                            ;
; 25                                           ; 8                             ;
; 26                                           ; 8                             ;
; 27                                           ; 5                             ;
; 28                                           ; 2                             ;
; 29                                           ; 9                             ;
; 30                                           ; 3                             ;
; 31                                           ; 3                             ;
; 32                                           ; 11                            ;
+----------------------------------------------+-------------------------------+


+---------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                         ;
+-------------------------------------------------+-------------------------------+
; Number of Signals Sourced Out  (Average = 6.51) ; Number of LABs  (Total = 203) ;
+-------------------------------------------------+-------------------------------+
; 0                                               ; 0                             ;
; 1                                               ; 22                            ;
; 2                                               ; 31                            ;
; 3                                               ; 35                            ;
; 4                                               ; 25                            ;
; 5                                               ; 11                            ;
; 6                                               ; 3                             ;
; 7                                               ; 5                             ;
; 8                                               ; 5                             ;
; 9                                               ; 6                             ;
; 10                                              ; 3                             ;
; 11                                              ; 10                            ;
; 12                                              ; 7                             ;
; 13                                              ; 11                            ;
; 14                                              ; 12                            ;
; 15                                              ; 2                             ;
; 16                                              ; 10                            ;
; 17                                              ; 1                             ;
; 18                                              ; 0                             ;
; 19                                              ; 2                             ;
; 20                                              ; 0                             ;
; 21                                              ; 0                             ;
; 22                                              ; 0                             ;
; 23                                              ; 1                             ;
; 24                                              ; 0                             ;
; 25                                              ; 0                             ;
; 26                                              ; 0                             ;
; 27                                              ; 1                             ;
+-------------------------------------------------+-------------------------------+


+------------------------------------------------------------------------------+
; LAB Distinct Inputs                                                          ;
+----------------------------------------------+-------------------------------+
; Number of Distinct Inputs  (Average = 10.65) ; Number of LABs  (Total = 203) ;
+----------------------------------------------+-------------------------------+
; 0                                            ; 0                             ;
; 1                                            ; 2                             ;
; 2                                            ; 17                            ;
; 3                                            ; 16                            ;
; 4                                            ; 17                            ;
; 5                                            ; 9                             ;
; 6                                            ; 7                             ;
; 7                                            ; 12                            ;
; 8                                            ; 13                            ;
; 9                                            ; 16                            ;
; 10                                           ; 4                             ;
; 11                                           ; 5                             ;
; 12                                           ; 10                            ;
; 13                                           ; 7                             ;
; 14                                           ; 5                             ;
; 15                                           ; 5                             ;
; 16                                           ; 17                            ;
; 17                                           ; 3                             ;
; 18                                           ; 5                             ;
; 19                                           ; 6                             ;
; 20                                           ; 7                             ;
; 21                                           ; 3                             ;
; 22                                           ; 1                             ;
; 23                                           ; 4                             ;
; 24                                           ; 3                             ;
; 25                                           ; 2                             ;
; 26                                           ; 1                             ;
; 27                                           ; 3                             ;
; 28                                           ; 0                             ;
; 29                                           ; 0                             ;
; 30                                           ; 0                             ;
; 31                                           ; 0                             ;
; 32                                           ; 1                             ;
; 33                                           ; 0                             ;
; 34                                           ; 1                             ;
+----------------------------------------------+-------------------------------+


+------------------------------------------+
; I/O Rules Summary                        ;
+----------------------------------+-------+
; I/O Rules Statistic              ; Total ;
+----------------------------------+-------+
; Total I/O Rules                  ; 30    ;
; Number of I/O Rules Passed       ; 12    ;
; Number of I/O Rules Failed       ; 0     ;
; Number of I/O Rules Unchecked    ; 0     ;
; Number of I/O Rules Inapplicable ; 18    ;
+----------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Pin/Rules           ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Total Pass          ; 7            ; 0            ; 7            ; 0            ; 0            ; 48        ; 7            ; 0            ; 48        ; 48        ; 0            ; 43           ; 0            ; 0            ; 1            ; 0            ; 43           ; 1            ; 0            ; 0            ; 0            ; 43           ; 0            ; 0            ; 0            ; 0            ; 0            ; 48        ; 0            ; 0            ;
; Total Unchecked     ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Total Inapplicable  ; 41           ; 48           ; 41           ; 48           ; 48           ; 0         ; 41           ; 48           ; 0         ; 0         ; 48           ; 5            ; 48           ; 48           ; 47           ; 48           ; 5            ; 47           ; 48           ; 48           ; 48           ; 5            ; 48           ; 48           ; 48           ; 48           ; 48           ; 0         ; 48           ; 48           ;
; Total Fail          ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; error_out           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[20]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[19]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[18]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[17]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[16]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[15]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[14]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[13]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[12]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[11]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[10]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[9]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[8]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[7]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[6]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[5]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[4]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[3]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[2]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[1]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; quotient[0]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[20]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[19]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[18]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[17]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[16]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[15]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[14]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[13]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[12]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[11]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[10]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[9]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[8]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[7]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[6]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[5]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[4]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[3]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[2]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[1]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; test1[0]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; clk_in_16M          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tms ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tck ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tdi ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tdo ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+


+-------------------------------------------------------------------------------------------+
; Fitter Device Options                                                                     ;
+------------------------------------------------------------------+------------------------+
; Option                                                           ; Setting                ;
+------------------------------------------------------------------+------------------------+
; Enable user-supplied start-up clock (CLKUSR)                     ; Off                    ;
; Enable device-wide reset (DEV_CLRn)                              ; Off                    ;
; Enable device-wide output enable (DEV_OE)                        ; Off                    ;
; Enable INIT_DONE output                                          ; Off                    ;
; Configuration scheme                                             ; Internal Configuration ;
; Enable Error Detection CRC_ERROR pin                             ; Off                    ;
; Enable open drain on CRC_ERROR pin                               ; Off                    ;
; Enable nCONFIG, nSTATUS, and CONF_DONE pins                      ; On                     ;
; Enable JTAG pin sharing                                          ; Off                    ;
; Enable nCE pin                                                   ; Off                    ;
; Enable CONFIG_SEL pin                                            ; On                     ;
; Enable input tri-state on active configuration pins in user mode ; Off                    ;
; Configuration Voltage Level                                      ; Auto                   ;
; Force Configuration Voltage Level                                ; Off                    ;
; Data[0]                                                          ; Unreserved             ;
; Data[1]/ASDO                                                     ; Unreserved             ;
; FLASH_nCE/nCSO                                                   ; Unreserved             ;
; DCLK                                                             ; Unreserved             ;
+------------------------------------------------------------------+------------------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; -40 °C ;
; High Junction Temperature ; 100 °C ;
+---------------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Summary                                                                                             ;
+-----------------------------------------------------------+-----------------------------------------------------------+-------------------+
; Source Clock(s)                                           ; Destination Clock(s)                                      ; Delay Added in ns ;
+-----------------------------------------------------------+-----------------------------------------------------------+-------------------+
; a_pll_220_110|altpll_component|auto_generated|pll1|clk[0] ; a_pll_220_110|altpll_component|auto_generated|pll1|clk[0] ; 3.5               ;
; altera_reserved_tck                                       ; altera_reserved_tck                                       ; 3.1               ;
+-----------------------------------------------------------+-----------------------------------------------------------+-------------------+
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
; Source Register                                                                                                                                                                                                                       ; Destination Register                                                                                                                                                                                                                     ; Delay Added in ns ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][31]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a31~porta_datain_reg0               ; 0.407             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][25]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a25~porta_datain_reg0               ; 0.407             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][40]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a40~porta_datain_reg0               ; 0.268             ;
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFNumerator[5]                                                                                    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFStage[13]                                                                                          ; 0.179             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][27]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a27~porta_datain_reg0               ; 0.165             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][24]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a24~porta_datain_reg0               ; 0.165             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][20]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a20~porta_datain_reg0               ; 0.165             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[59] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[58]    ; 0.143             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[50] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[49]    ; 0.143             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[0]     ; 0.143             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[34] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[33]    ; 0.141             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[18] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[17]    ; 0.141             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[5]                                                                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[5]                                                                                                     ; 0.141             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[4]                                                                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[4]                                                                                                     ; 0.141             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[3]                                                                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[3]                                                                                                     ; 0.141             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[1]                                                                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[1]                                                                                                     ; 0.141             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[0]                                                                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[0]                                                                                                     ; 0.141             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[12]                                                                          ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[12]                                                                                                    ; 0.141             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][70]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a70~porta_datain_reg0               ; 0.133             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[22]                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[22] ; 0.132             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][82]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a82~porta_datain_reg0               ; 0.131             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][79]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a79~porta_datain_reg0               ; 0.131             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][10]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a10~porta_datain_reg0               ; 0.131             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][9]                                                                                                ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a9~porta_datain_reg0                ; 0.131             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][30]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a30~porta_datain_reg0               ; 0.129             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][29]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a29~porta_datain_reg0               ; 0.129             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][26]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a26~porta_datain_reg0               ; 0.129             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][34]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a34~porta_datain_reg0               ; 0.120             ;
; test_div_1:inst|S_counter_reg[2]                                                                                                                                                                                                      ; test_div_1:inst|S_state_reg.st0                                                                                                                                                                                                          ; 0.118             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][33]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a33~porta_datain_reg0               ; 0.105             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[5] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[4]    ; 0.101             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[21]                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[21] ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[20]                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[20] ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[19]                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[19] ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[17]                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[17] ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[16]                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[16] ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[15]                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[15] ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[14]                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[14] ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[13]                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[13] ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[12]                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[12] ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[11]                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[11] ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[9]                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[9]  ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[8]                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[8]  ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xq[7]                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[7]  ; 0.099             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][23]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a23~porta_datain_reg0               ; 0.094             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][21]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a21~porta_datain_reg0               ; 0.091             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][64]                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ram_block1a64~porta_datain_reg0               ; 0.042             ;
; test_div_1:inst|S_state_reg.idle                                                                                                                                                                                                      ; test_div_1:inst|S_state_reg.st1                                                                                                                                                                                                          ; 0.032             ;
; test_div_1:inst|S_counter_reg[4]                                                                                                                                                                                                      ; test_div_1:inst|S_counter_reg[4]                                                                                                                                                                                                         ; 0.031             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:done                                                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:collecting_post_data_var                                          ; 0.013             ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
Note: This table only shows the top 50 path(s) that have the largest delay added for hold.


+-----------------+
; Fitter Messages ;
+-----------------+
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (119006): Selected device 10M08SCM153I7G for design "fs20_01"
Info (21077): Low junction temperature is -40 degrees C
Info (21077): High junction temperature is 100 degrees C
Info (15535): Implemented PLL "alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated|pll1" as MAX 10 PLL type File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_pll_220_110_altpll.v Line: 46
    Info (15099): Implementing clock multiplication of 6, clock division of 1, and phase shift of 0 degrees (0 ps) for alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated|wire_pll1_clk[0] port File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_pll_220_110_altpll.v Line: 46
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Critical Warning (16562): Review the PowerPlay Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info (176445): Device 10M04SCM153I7G is compatible
    Info (176445): Device 10M02SCM153I7G is compatible
Info (169124): Fitter converted 4 user pins into dedicated programming pins
    Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8
    Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location E8
    Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location D6
    Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location E6
Info (169141): DATA[0] dual-purpose pin not reserved
Info (12825): Data[1]/ASDO dual-purpose pin not reserved
Info (12825): nCSO dual-purpose pin not reserved
Info (12825): DCLK dual-purpose pin not reserved
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning (169085): No exact pin location assignment(s) for 37 pins of 44 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity sld_hub
        Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz   
        Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck}
Info (332104): Reading SDC File: 'SDC1.sdc'
Warning (332043): Overwriting existing clock: altera_reserved_tck
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {a_pll_220_110|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 6 -duty_cycle 50.00 -name {a_pll_220_110|altpll_component|auto_generated|pll1|clk[0]} {a_pll_220_110|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: altera_internal_jtag  from: tck  to: tckutap
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 3 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):   10.416 a_pll_220_110|altpll_component|auto_generated|pll1|clk[0]
    Info (332111):  100.000 altera_reserved_tck
    Info (332111):   62.500    clk_input
Info (176353): Automatically promoted node alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_1) File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_pll_220_110_altpll.v Line: 81
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info (176353): Automatically promoted node altera_internal_jtag~TCKUTAP 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all  File: d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd Line: 882
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]~0 File: d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd Line: 356
        Info (176357): Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~0 File: d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd Line: 638
        Info (176357): Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset File: d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd Line: 638
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176219): No registers were packed into other blocks
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info (176211): Number of I/O pins in group: 37 (unused VREF, 2.5V VCCIO, 0 input, 37 output, 0 bidirectional)
        Info (176212): I/O standards used: 2.5 V.
Info (176215): I/O bank details before I/O pin placement
    Info (176214): Statistics of I/O banks
        Info (176213): I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  8 pins available
        Info (176213): I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  6 pins available
        Info (176213): I/O bank number 2 does not use VREF pins and has 2.5V VCCIO pins. 2 total pin(s) used --  8 pins available
        Info (176213): I/O bank number 3 does not use VREF pins and has 2.5V VCCIO pins. 2 total pin(s) used --  26 pins available
        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available
        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  16 pins available
        Info (176213): I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 7 total pin(s) used --  21 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:07
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:11
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 4% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 9% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info (170201): Optimizations that may affect the design's routability were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:05
Info (11888): Total time spent on timing analysis during the Fitter is 3.12 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:07
Warning (169177): 1 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
    Info (169178): Pin clk_in_16M uses I/O standard 3.3-V LVCMOS at K4
Info (144001): Generated suppressed messages file E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/output_files/fs20_01.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
    Info: Peak virtual memory: 5424 megabytes
    Info: Processing ended: Wed Sep 16 13:24:11 2020
    Info: Elapsed time: 00:00:45
    Info: Total CPU time (on all processors): 00:00:51


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/output_files/fs20_01.fit.smsg.


