--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_A="NONE" BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="MAX 10" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=1024 NUMWORDS_B=1024 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=134 WIDTH_B=134 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=10 WIDTHAD_B=10 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 16.1 cbx_altera_syncram_nd_impl 2016:10:24:15:04:16:SJ cbx_altsyncram 2016:10:24:15:04:16:SJ cbx_cycloneii 2016:10:24:15:04:16:SJ cbx_lpm_add_sub 2016:10:24:15:04:16:SJ cbx_lpm_compare 2016:10:24:15:04:16:SJ cbx_lpm_decode 2016:10:24:15:04:16:SJ cbx_lpm_mux 2016:10:24:15:04:16:SJ cbx_mgl 2016:10:24:15:05:03:SJ cbx_nadder 2016:10:24:15:04:16:SJ cbx_stratix 2016:10:24:15:04:16:SJ cbx_stratixii 2016:10:24:15:04:16:SJ cbx_stratixiii 2016:10:24:15:04:16:SJ cbx_stratixv 2016:10:24:15:04:16:SJ cbx_util_mgl 2016:10:24:15:04:16:SJ  VERSION_END


-- Copyright (C) 2016  Intel Corporation. All rights reserved.
--  Your use of Intel Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Intel Program License 
--  Subscription Agreement, the Intel Quartus Prime License Agreement,
--  the Intel MegaCore Function License Agreement, or other 
--  applicable license agreement, including, without limitation, 
--  that your use is for the sole purpose of programming logic 
--  devices manufactured by Intel and sold by Intel or its 
--  authorized distributors.  Please refer to the applicable 
--  agreement for further details.


FUNCTION fiftyfivenm_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = M9K 15 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_9o14
( 
	address_a[9..0]	:	input;
	address_b[9..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	clocken1	:	input;
	data_a[133..0]	:	input;
	q_b[133..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	ram_block1a0 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a1 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a2 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a3 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 3,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a4 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a5 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a6 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a7 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a8 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 8,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a9 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 9,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a10 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 10,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a11 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 11,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a12 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 12,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a13 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 13,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a14 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 14,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a15 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 15,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a16 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 16,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a17 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 17,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a18 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 18,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a19 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 19,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a20 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 20,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a21 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 21,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a22 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 22,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a23 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 23,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a24 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 24,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a25 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 25,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a26 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 26,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a27 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 27,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a28 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 28,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a29 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 29,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a30 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 30,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a31 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 31,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a32 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 32,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 32,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a33 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 33,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 33,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a34 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 34,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 34,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a35 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 35,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 35,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a36 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 36,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 36,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a37 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 37,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 37,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a38 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 38,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 38,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a39 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 39,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 39,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a40 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 40,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 40,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a41 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 41,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 41,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a42 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 42,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 42,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a43 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 43,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 43,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a44 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 44,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 44,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a45 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 45,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 45,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a46 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 46,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 46,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a47 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 47,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 47,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a48 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 48,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 48,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a49 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 49,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 49,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a50 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 50,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 50,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a51 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 51,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 51,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a52 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 52,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 52,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a53 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 53,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 53,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a54 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 54,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 54,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a55 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 55,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 55,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a56 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 56,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 56,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a57 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 57,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 57,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a58 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 58,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 58,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a59 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 59,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 59,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a60 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 60,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 60,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a61 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 61,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 61,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a62 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 62,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 62,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a63 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 63,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 63,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a64 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 64,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 64,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a65 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 65,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 65,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a66 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 66,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 66,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a67 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 67,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 67,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a68 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 68,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 68,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a69 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 69,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 69,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a70 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 70,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 70,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a71 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 71,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 71,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a72 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 72,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 72,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a73 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 73,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 73,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a74 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 74,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 74,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a75 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 75,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 75,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a76 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 76,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 76,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a77 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 77,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 77,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a78 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 78,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 78,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a79 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 79,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 79,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a80 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 80,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 80,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a81 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 81,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 81,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a82 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 82,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 82,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a83 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 83,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 83,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a84 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 84,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 84,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a85 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 85,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 85,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a86 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 86,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 86,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a87 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 87,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 87,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a88 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 88,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 88,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a89 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 89,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 89,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a90 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 90,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 90,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a91 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 91,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 91,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a92 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 92,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 92,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a93 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 93,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 93,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a94 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 94,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 94,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a95 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 95,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 95,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a96 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 96,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 96,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a97 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 97,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 97,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a98 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 98,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 98,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a99 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 99,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 99,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a100 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 100,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 100,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a101 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 101,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 101,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a102 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 102,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 102,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a103 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 103,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 103,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a104 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 104,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 104,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a105 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 105,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 105,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a106 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 106,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 106,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a107 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 107,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 107,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a108 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 108,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 108,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a109 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 109,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 109,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a110 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 110,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 110,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a111 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 111,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 111,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a112 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 112,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 112,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a113 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 113,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 113,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a114 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 114,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 114,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a115 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 115,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 115,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a116 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 116,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 116,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a117 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 117,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 117,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a118 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 118,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 118,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a119 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 119,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 119,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a120 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 120,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 120,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a121 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 121,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 121,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a122 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 122,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 122,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a123 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 123,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 123,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a124 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 124,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 124,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a125 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 125,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 125,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a126 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 126,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 126,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a127 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 127,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 127,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a128 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 128,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 128,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a129 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 129,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 129,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a130 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 130,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 130,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a131 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 131,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 131,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a132 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 132,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 132,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a133 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "ena1",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 133,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 134,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 10,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 133,
			PORT_B_LAST_ADDRESS = 1023,
			PORT_B_LOGICAL_RAM_DEPTH = 1024,
			PORT_B_LOGICAL_RAM_WIDTH = 134,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	address_a_wire[9..0]	: WIRE;
	address_b_wire[9..0]	: WIRE;

BEGIN 
	ram_block1a[133..0].clk0 = clock0;
	ram_block1a[133..0].clk1 = clock1;
	ram_block1a[133..0].ena0 = wren_a;
	ram_block1a[133..0].ena1 = clocken1;
	ram_block1a[133..0].portaaddr[] = ( address_a_wire[9..0]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[1..1]);
	ram_block1a[2].portadatain[] = ( data_a[2..2]);
	ram_block1a[3].portadatain[] = ( data_a[3..3]);
	ram_block1a[4].portadatain[] = ( data_a[4..4]);
	ram_block1a[5].portadatain[] = ( data_a[5..5]);
	ram_block1a[6].portadatain[] = ( data_a[6..6]);
	ram_block1a[7].portadatain[] = ( data_a[7..7]);
	ram_block1a[8].portadatain[] = ( data_a[8..8]);
	ram_block1a[9].portadatain[] = ( data_a[9..9]);
	ram_block1a[10].portadatain[] = ( data_a[10..10]);
	ram_block1a[11].portadatain[] = ( data_a[11..11]);
	ram_block1a[12].portadatain[] = ( data_a[12..12]);
	ram_block1a[13].portadatain[] = ( data_a[13..13]);
	ram_block1a[14].portadatain[] = ( data_a[14..14]);
	ram_block1a[15].portadatain[] = ( data_a[15..15]);
	ram_block1a[16].portadatain[] = ( data_a[16..16]);
	ram_block1a[17].portadatain[] = ( data_a[17..17]);
	ram_block1a[18].portadatain[] = ( data_a[18..18]);
	ram_block1a[19].portadatain[] = ( data_a[19..19]);
	ram_block1a[20].portadatain[] = ( data_a[20..20]);
	ram_block1a[21].portadatain[] = ( data_a[21..21]);
	ram_block1a[22].portadatain[] = ( data_a[22..22]);
	ram_block1a[23].portadatain[] = ( data_a[23..23]);
	ram_block1a[24].portadatain[] = ( data_a[24..24]);
	ram_block1a[25].portadatain[] = ( data_a[25..25]);
	ram_block1a[26].portadatain[] = ( data_a[26..26]);
	ram_block1a[27].portadatain[] = ( data_a[27..27]);
	ram_block1a[28].portadatain[] = ( data_a[28..28]);
	ram_block1a[29].portadatain[] = ( data_a[29..29]);
	ram_block1a[30].portadatain[] = ( data_a[30..30]);
	ram_block1a[31].portadatain[] = ( data_a[31..31]);
	ram_block1a[32].portadatain[] = ( data_a[32..32]);
	ram_block1a[33].portadatain[] = ( data_a[33..33]);
	ram_block1a[34].portadatain[] = ( data_a[34..34]);
	ram_block1a[35].portadatain[] = ( data_a[35..35]);
	ram_block1a[36].portadatain[] = ( data_a[36..36]);
	ram_block1a[37].portadatain[] = ( data_a[37..37]);
	ram_block1a[38].portadatain[] = ( data_a[38..38]);
	ram_block1a[39].portadatain[] = ( data_a[39..39]);
	ram_block1a[40].portadatain[] = ( data_a[40..40]);
	ram_block1a[41].portadatain[] = ( data_a[41..41]);
	ram_block1a[42].portadatain[] = ( data_a[42..42]);
	ram_block1a[43].portadatain[] = ( data_a[43..43]);
	ram_block1a[44].portadatain[] = ( data_a[44..44]);
	ram_block1a[45].portadatain[] = ( data_a[45..45]);
	ram_block1a[46].portadatain[] = ( data_a[46..46]);
	ram_block1a[47].portadatain[] = ( data_a[47..47]);
	ram_block1a[48].portadatain[] = ( data_a[48..48]);
	ram_block1a[49].portadatain[] = ( data_a[49..49]);
	ram_block1a[50].portadatain[] = ( data_a[50..50]);
	ram_block1a[51].portadatain[] = ( data_a[51..51]);
	ram_block1a[52].portadatain[] = ( data_a[52..52]);
	ram_block1a[53].portadatain[] = ( data_a[53..53]);
	ram_block1a[54].portadatain[] = ( data_a[54..54]);
	ram_block1a[55].portadatain[] = ( data_a[55..55]);
	ram_block1a[56].portadatain[] = ( data_a[56..56]);
	ram_block1a[57].portadatain[] = ( data_a[57..57]);
	ram_block1a[58].portadatain[] = ( data_a[58..58]);
	ram_block1a[59].portadatain[] = ( data_a[59..59]);
	ram_block1a[60].portadatain[] = ( data_a[60..60]);
	ram_block1a[61].portadatain[] = ( data_a[61..61]);
	ram_block1a[62].portadatain[] = ( data_a[62..62]);
	ram_block1a[63].portadatain[] = ( data_a[63..63]);
	ram_block1a[64].portadatain[] = ( data_a[64..64]);
	ram_block1a[65].portadatain[] = ( data_a[65..65]);
	ram_block1a[66].portadatain[] = ( data_a[66..66]);
	ram_block1a[67].portadatain[] = ( data_a[67..67]);
	ram_block1a[68].portadatain[] = ( data_a[68..68]);
	ram_block1a[69].portadatain[] = ( data_a[69..69]);
	ram_block1a[70].portadatain[] = ( data_a[70..70]);
	ram_block1a[71].portadatain[] = ( data_a[71..71]);
	ram_block1a[72].portadatain[] = ( data_a[72..72]);
	ram_block1a[73].portadatain[] = ( data_a[73..73]);
	ram_block1a[74].portadatain[] = ( data_a[74..74]);
	ram_block1a[75].portadatain[] = ( data_a[75..75]);
	ram_block1a[76].portadatain[] = ( data_a[76..76]);
	ram_block1a[77].portadatain[] = ( data_a[77..77]);
	ram_block1a[78].portadatain[] = ( data_a[78..78]);
	ram_block1a[79].portadatain[] = ( data_a[79..79]);
	ram_block1a[80].portadatain[] = ( data_a[80..80]);
	ram_block1a[81].portadatain[] = ( data_a[81..81]);
	ram_block1a[82].portadatain[] = ( data_a[82..82]);
	ram_block1a[83].portadatain[] = ( data_a[83..83]);
	ram_block1a[84].portadatain[] = ( data_a[84..84]);
	ram_block1a[85].portadatain[] = ( data_a[85..85]);
	ram_block1a[86].portadatain[] = ( data_a[86..86]);
	ram_block1a[87].portadatain[] = ( data_a[87..87]);
	ram_block1a[88].portadatain[] = ( data_a[88..88]);
	ram_block1a[89].portadatain[] = ( data_a[89..89]);
	ram_block1a[90].portadatain[] = ( data_a[90..90]);
	ram_block1a[91].portadatain[] = ( data_a[91..91]);
	ram_block1a[92].portadatain[] = ( data_a[92..92]);
	ram_block1a[93].portadatain[] = ( data_a[93..93]);
	ram_block1a[94].portadatain[] = ( data_a[94..94]);
	ram_block1a[95].portadatain[] = ( data_a[95..95]);
	ram_block1a[96].portadatain[] = ( data_a[96..96]);
	ram_block1a[97].portadatain[] = ( data_a[97..97]);
	ram_block1a[98].portadatain[] = ( data_a[98..98]);
	ram_block1a[99].portadatain[] = ( data_a[99..99]);
	ram_block1a[100].portadatain[] = ( data_a[100..100]);
	ram_block1a[101].portadatain[] = ( data_a[101..101]);
	ram_block1a[102].portadatain[] = ( data_a[102..102]);
	ram_block1a[103].portadatain[] = ( data_a[103..103]);
	ram_block1a[104].portadatain[] = ( data_a[104..104]);
	ram_block1a[105].portadatain[] = ( data_a[105..105]);
	ram_block1a[106].portadatain[] = ( data_a[106..106]);
	ram_block1a[107].portadatain[] = ( data_a[107..107]);
	ram_block1a[108].portadatain[] = ( data_a[108..108]);
	ram_block1a[109].portadatain[] = ( data_a[109..109]);
	ram_block1a[110].portadatain[] = ( data_a[110..110]);
	ram_block1a[111].portadatain[] = ( data_a[111..111]);
	ram_block1a[112].portadatain[] = ( data_a[112..112]);
	ram_block1a[113].portadatain[] = ( data_a[113..113]);
	ram_block1a[114].portadatain[] = ( data_a[114..114]);
	ram_block1a[115].portadatain[] = ( data_a[115..115]);
	ram_block1a[116].portadatain[] = ( data_a[116..116]);
	ram_block1a[117].portadatain[] = ( data_a[117..117]);
	ram_block1a[118].portadatain[] = ( data_a[118..118]);
	ram_block1a[119].portadatain[] = ( data_a[119..119]);
	ram_block1a[120].portadatain[] = ( data_a[120..120]);
	ram_block1a[121].portadatain[] = ( data_a[121..121]);
	ram_block1a[122].portadatain[] = ( data_a[122..122]);
	ram_block1a[123].portadatain[] = ( data_a[123..123]);
	ram_block1a[124].portadatain[] = ( data_a[124..124]);
	ram_block1a[125].portadatain[] = ( data_a[125..125]);
	ram_block1a[126].portadatain[] = ( data_a[126..126]);
	ram_block1a[127].portadatain[] = ( data_a[127..127]);
	ram_block1a[128].portadatain[] = ( data_a[128..128]);
	ram_block1a[129].portadatain[] = ( data_a[129..129]);
	ram_block1a[130].portadatain[] = ( data_a[130..130]);
	ram_block1a[131].portadatain[] = ( data_a[131..131]);
	ram_block1a[132].portadatain[] = ( data_a[132..132]);
	ram_block1a[133].portadatain[] = ( data_a[133..133]);
	ram_block1a[133..0].portawe = wren_a;
	ram_block1a[133..0].portbaddr[] = ( address_b_wire[9..0]);
	ram_block1a[133..0].portbre = B"11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111";
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_b[] = ( ram_block1a[133..0].portbdataout[0..0]);
END;
--VALID FILE
