{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1600225350854 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1600225350872 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 11:02:30 2020 " "Processing started: Wed Sep 16 11:02:30 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1600225350872 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225350872 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fs20_01 -c fs20_01 " "Command: quartus_map --read_settings_files=on --write_settings_files=off fs20_01 -c fs20_01" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225350872 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1600225351728 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1600225351728 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fs20_01.bdf 1 1 " "Found 1 design units, including 1 entities, in source file fs20_01.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 fs20_01 " "Found entity 1: fs20_01" {  } { { "fs20_01.bdf" "" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225367683 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225367683 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "inc_div.vhd " "Can't analyze file -- file inc_div.vhd is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1600225367693 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "lut_inc.vhd " "Can't analyze file -- file lut_inc.vhd is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1600225367704 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alt_pll_220_110.vhd 2 1 " "Found 2 design units, including 1 entities, in source file alt_pll_220_110.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_pll_220_110-SYN " "Found design unit 1: alt_pll_220_110-SYN" {  } { { "alt_pll_220_110.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/alt_pll_220_110.vhd" 53 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225368937 ""} { "Info" "ISGN_ENTITY_NAME" "1 alt_pll_220_110 " "Found entity 1: alt_pll_220_110" {  } { { "alt_pll_220_110.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/alt_pll_220_110.vhd" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225368937 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225368937 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "lut1um.vhd " "Can't analyze file -- file lut1um.vhd is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1600225368945 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "ram_1.vhd " "Can't analyze file -- file ram_1.vhd is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1600225368966 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "ram_2port_1.vhd " "Can't analyze file -- file ram_2port_1.vhd is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1600225368972 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "lut_ram.vhd " "Can't analyze file -- file lut_ram.vhd is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1600225368977 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div_no_pipeline.vhd 2 1 " "Found 2 design units, including 1 entities, in source file div_no_pipeline.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div_no_pipeline-SYN " "Found design unit 1: div_no_pipeline-SYN" {  } { { "div_no_pipeline.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/div_no_pipeline.vhd" 54 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225368981 ""} { "Info" "ISGN_ENTITY_NAME" "1 div_no_pipeline " "Found entity 1: div_no_pipeline" {  } { { "div_no_pipeline.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/div_no_pipeline.vhd" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225368981 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225368981 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "inc_div_test.vhd 2 1 " "Found 2 design units, including 1 entities, in source file inc_div_test.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 inc_div_test-SYN " "Found design unit 1: inc_div_test-SYN" {  } { { "inc_div_test.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/inc_div_test.vhd" 56 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225368986 ""} { "Info" "ISGN_ENTITY_NAME" "1 inc_div_test " "Found entity 1: inc_div_test" {  } { { "inc_div_test.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/inc_div_test.vhd" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225368986 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225368986 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test_div_1.vhd 2 1 " "Found 2 design units, including 1 entities, in source file test_div_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 test_div_1-Behavioral " "Found design unit 1: test_div_1-Behavioral" {  } { { "test_div_1.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/test_div_1.vhd" 52 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225368994 ""} { "Info" "ISGN_ENTITY_NAME" "1 test_div_1 " "Found entity 1: test_div_1" {  } { { "test_div_1.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/test_div_1.vhd" 31 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225368994 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225368994 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "fs20_01 " "Elaborating entity \"fs20_01\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1600225370283 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "test_div_1 test_div_1:inst " "Elaborating entity \"test_div_1\" for hierarchy \"test_div_1:inst\"" {  } { { "fs20_01.bdf" "inst" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { { 160 440 656 272 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225370343 ""}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "S_error_out_reg test_div_1.vhd(111) " "VHDL Process Statement warning at test_div_1.vhd(111): signal \"S_error_out_reg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "test_div_1.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/test_div_1.vhd" 111 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "Analysis & Synthesis" 0 -1 1600225370353 "|fs20_01|test_div_1:inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_pll_220_110 alt_pll_220_110:a_pll_220_110 " "Elaborating entity \"alt_pll_220_110\" for hierarchy \"alt_pll_220_110:a_pll_220_110\"" {  } { { "fs20_01.bdf" "a_pll_220_110" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { { -128 344 600 24 "a_pll_220_110" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225370414 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll alt_pll_220_110:a_pll_220_110\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"alt_pll_220_110:a_pll_220_110\|altpll:altpll_component\"" {  } { { "alt_pll_220_110.vhd" "altpll_component" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/alt_pll_220_110.vhd" 139 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225370557 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "alt_pll_220_110:a_pll_220_110\|altpll:altpll_component " "Elaborated megafunction instantiation \"alt_pll_220_110:a_pll_220_110\|altpll:altpll_component\"" {  } { { "alt_pll_220_110.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/alt_pll_220_110.vhd" 139 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225370600 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "alt_pll_220_110:a_pll_220_110\|altpll:altpll_component " "Instantiated megafunction \"alt_pll_220_110:a_pll_220_110\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 6 " "Parameter \"clk0_multiply_by\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 62500 " "Parameter \"inclk0_input_frequency\" = \"62500\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family MAX 10 " "Parameter \"intended_device_family\" = \"MAX 10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=alt_pll_220_110 " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=alt_pll_220_110\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Parameter \"port_clk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370602 ""}  } { { "alt_pll_220_110.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/alt_pll_220_110.vhd" 139 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1600225370602 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_pll_220_110_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_pll_220_110_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_pll_220_110_altpll " "Found entity 1: alt_pll_220_110_altpll" {  } { { "db/alt_pll_220_110_altpll.v" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_pll_220_110_altpll.v" 30 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225370722 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225370722 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_pll_220_110_altpll alt_pll_220_110:a_pll_220_110\|altpll:altpll_component\|alt_pll_220_110_altpll:auto_generated " "Elaborating entity \"alt_pll_220_110_altpll\" for hierarchy \"alt_pll_220_110:a_pll_220_110\|altpll:altpll_component\|alt_pll_220_110_altpll:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "d:/intelfpga/16.1/quartus/libraries/megafunctions/altpll.tdf" 898 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225370723 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_div_test inc_div_test:inst1 " "Elaborating entity \"inc_div_test\" for hierarchy \"inc_div_test:inst1\"" {  } { { "fs20_01.bdf" "inst1" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { { 344 472 648 456 "inst1" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225370800 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component " "Elaborating entity \"lpm_divide\" for hierarchy \"inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\"" {  } { { "inc_div_test.vhd" "LPM_DIVIDE_component" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/inc_div_test.vhd" 87 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225370914 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component " "Elaborated megafunction instantiation \"inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\"" {  } { { "inc_div_test.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/inc_div_test.vhd" 87 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225370946 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component " "Instantiated megafunction \"inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_drepresentation UNSIGNED " "Parameter \"lpm_drepresentation\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint MAXIMIZE_SPEED=5,LPM_REMAINDERPOSITIVE=TRUE " "Parameter \"lpm_hint\" = \"MAXIMIZE_SPEED=5,LPM_REMAINDERPOSITIVE=TRUE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_nrepresentation UNSIGNED " "Parameter \"lpm_nrepresentation\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 2 " "Parameter \"lpm_pipeline\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_DIVIDE " "Parameter \"lpm_type\" = \"LPM_DIVIDE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthd 12 " "Parameter \"lpm_widthd\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthn 21 " "Parameter \"lpm_widthn\" = \"21\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225370946 ""}  } { { "inc_div_test.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/inc_div_test.vhd" 87 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1600225370946 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_uft.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_uft.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_uft " "Found entity 1: lpm_divide_uft" {  } { { "db/lpm_divide_uft.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/lpm_divide_uft.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225371037 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225371037 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide_uft inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_uft:auto_generated " "Elaborating entity \"lpm_divide_uft\" for hierarchy \"inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_uft:auto_generated\"" {  } { { "lpm_divide.tdf" "auto_generated" { Text "d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_divide.tdf" 148 9 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225371038 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_0qi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_0qi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_0qi " "Found entity 1: sign_div_unsign_0qi" {  } { { "db/sign_div_unsign_0qi.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/sign_div_unsign_0qi.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225371130 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225371130 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_div_unsign_0qi inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_uft:auto_generated\|sign_div_unsign_0qi:divider " "Elaborating entity \"sign_div_unsign_0qi\" for hierarchy \"inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_uft:auto_generated\|sign_div_unsign_0qi:divider\"" {  } { { "db/lpm_divide_uft.tdf" "divider" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/lpm_divide_uft.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225371132 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_eqf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_eqf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_eqf " "Found entity 1: alt_u_div_eqf" {  } { { "db/alt_u_div_eqf.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_u_div_eqf.tdf" 30 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225371284 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225371284 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_u_div_eqf inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_uft:auto_generated\|sign_div_unsign_0qi:divider\|alt_u_div_eqf:divider " "Elaborating entity \"alt_u_div_eqf\" for hierarchy \"inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_uft:auto_generated\|sign_div_unsign_0qi:divider\|alt_u_div_eqf:divider\"" {  } { { "db/sign_div_unsign_0qi.tdf" "divider" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/sign_div_unsign_0qi.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225371287 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_t3c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_t3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_t3c " "Found entity 1: add_sub_t3c" {  } { { "db/add_sub_t3c.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/add_sub_t3c.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225371612 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225371612 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_t3c inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_uft:auto_generated\|sign_div_unsign_0qi:divider\|alt_u_div_eqf:divider\|add_sub_t3c:add_sub_0 " "Elaborating entity \"add_sub_t3c\" for hierarchy \"inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_uft:auto_generated\|sign_div_unsign_0qi:divider\|alt_u_div_eqf:divider\|add_sub_t3c:add_sub_0\"" {  } { { "db/alt_u_div_eqf.tdf" "add_sub_0" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_u_div_eqf.tdf" 47 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225371614 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_u3c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_u3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_u3c " "Found entity 1: add_sub_u3c" {  } { { "db/add_sub_u3c.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/add_sub_u3c.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225371790 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225371790 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_u3c inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_uft:auto_generated\|sign_div_unsign_0qi:divider\|alt_u_div_eqf:divider\|add_sub_u3c:add_sub_1 " "Elaborating entity \"add_sub_u3c\" for hierarchy \"inc_div_test:inst1\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_uft:auto_generated\|sign_div_unsign_0qi:divider\|alt_u_div_eqf:divider\|add_sub_u3c:add_sub_1\"" {  } { { "db/alt_u_div_eqf.tdf" "add_sub_1" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_u_div_eqf.tdf" 48 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225371791 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_no_pipeline div_no_pipeline:no_pipeline " "Elaborating entity \"div_no_pipeline\" for hierarchy \"div_no_pipeline:no_pipeline\"" {  } { { "fs20_01.bdf" "no_pipeline" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { { 544 456 632 640 "no_pipeline" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225371856 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component " "Elaborating entity \"lpm_divide\" for hierarchy \"div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component\"" {  } { { "div_no_pipeline.vhd" "LPM_DIVIDE_component" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/div_no_pipeline.vhd" 82 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225372630 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component " "Elaborated megafunction instantiation \"div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component\"" {  } { { "div_no_pipeline.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/div_no_pipeline.vhd" 82 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225372690 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component " "Instantiated megafunction \"div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_drepresentation UNSIGNED " "Parameter \"lpm_drepresentation\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225372690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint MAXIMIZE_SPEED=5,LPM_REMAINDERPOSITIVE=TRUE " "Parameter \"lpm_hint\" = \"MAXIMIZE_SPEED=5,LPM_REMAINDERPOSITIVE=TRUE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225372690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_nrepresentation UNSIGNED " "Parameter \"lpm_nrepresentation\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225372690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_DIVIDE " "Parameter \"lpm_type\" = \"LPM_DIVIDE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225372690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthd 12 " "Parameter \"lpm_widthd\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225372690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthn 21 " "Parameter \"lpm_widthn\" = \"21\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600225372690 ""}  } { { "div_no_pipeline.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/div_no_pipeline.vhd" 82 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1600225372690 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_o0r.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_o0r.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_o0r " "Found entity 1: lpm_divide_o0r" {  } { { "db/lpm_divide_o0r.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/lpm_divide_o0r.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225372858 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225372858 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide_o0r div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_o0r:auto_generated " "Elaborating entity \"lpm_divide_o0r\" for hierarchy \"div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_o0r:auto_generated\"" {  } { { "lpm_divide.tdf" "auto_generated" { Text "d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_divide.tdf" 148 9 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225372859 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_5nh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_5nh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_5nh " "Found entity 1: sign_div_unsign_5nh" {  } { { "db/sign_div_unsign_5nh.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/sign_div_unsign_5nh.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225372961 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225372961 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_div_unsign_5nh div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_o0r:auto_generated\|sign_div_unsign_5nh:divider " "Elaborating entity \"sign_div_unsign_5nh\" for hierarchy \"div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_o0r:auto_generated\|sign_div_unsign_5nh:divider\"" {  } { { "db/lpm_divide_o0r.tdf" "divider" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/lpm_divide_o0r.tdf" 33 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225372964 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_kke.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_kke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_kke " "Found entity 1: alt_u_div_kke" {  } { { "db/alt_u_div_kke.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_u_div_kke.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225373126 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225373126 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_u_div_kke div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_o0r:auto_generated\|sign_div_unsign_5nh:divider\|alt_u_div_kke:divider " "Elaborating entity \"alt_u_div_kke\" for hierarchy \"div_no_pipeline:no_pipeline\|lpm_divide:LPM_DIVIDE_component\|lpm_divide_o0r:auto_generated\|sign_div_unsign_5nh:divider\|alt_u_div_kke:divider\"" {  } { { "db/sign_div_unsign_5nh.tdf" "divider" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/sign_div_unsign_5nh.tdf" 33 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225373128 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_am14.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_am14.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_am14 " "Found entity 1: altsyncram_am14" {  } { { "db/altsyncram_am14.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/altsyncram_am14.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225377544 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225377544 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_h7c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_h7c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_h7c " "Found entity 1: mux_h7c" {  } { { "db/mux_h7c.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/mux_h7c.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225378728 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225378728 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_3af.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_3af.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_3af " "Found entity 1: decode_3af" {  } { { "db/decode_3af.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/decode_3af.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225379088 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225379088 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_lrh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_lrh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_lrh " "Found entity 1: cntr_lrh" {  } { { "db/cntr_lrh.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_lrh.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225379559 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225379559 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_jrb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_jrb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_jrb " "Found entity 1: cmpr_jrb" {  } { { "db/cmpr_jrb.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cmpr_jrb.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225379772 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225379772 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_6ki.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_6ki.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_6ki " "Found entity 1: cntr_6ki" {  } { { "db/cntr_6ki.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_6ki.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225379970 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225379970 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_4rh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_4rh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_4rh " "Found entity 1: cntr_4rh" {  } { { "db/cntr_4rh.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_4rh.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225380209 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225380209 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_hrb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_hrb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_hrb " "Found entity 1: cmpr_hrb" {  } { { "db/cmpr_hrb.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cmpr_hrb.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225380318 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225380318 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_odi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_odi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_odi " "Found entity 1: cntr_odi" {  } { { "db/cntr_odi.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_odi.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225380619 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225380619 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_drb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_drb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_drb " "Found entity 1: cmpr_drb" {  } { { "db/cmpr_drb.tdf" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cmpr_drb.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225380786 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225380786 ""}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" {  } {  } 0 12033 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225382509 ""}
{ "Info" "ISCI_START_SUPER_FABRIC_GEN" "alt_sld_fab " "Starting IP generation for the debug fabric: alt_sld_fab." {  } {  } 0 11170 "Starting IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1600225382769 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "2020.09.16.11:03:09 Progress: Loading sld5df68646/alt_sld_fab_wrapper_hw.tcl " "2020.09.16.11:03:09 Progress: Loading sld5df68646/alt_sld_fab_wrapper_hw.tcl" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225389670 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225396026 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH " "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225396329 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\" " "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225404116 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\" " "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225404327 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\" " "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225404522 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\" " "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225404741 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\" " "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225404759 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files " "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225404768 ""}
{ "Info" "ISCI_END_SUPER_FABRIC_GEN" "alt_sld_fab " "Finished IP generation for the debug fabric: alt_sld_fab." {  } {  } 0 11171 "Finished IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1600225405544 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld5df68646/alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld5df68646/alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab " "Found entity 1: alt_sld_fab" {  } { { "db/ip/sld5df68646/alt_sld_fab.v" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/alt_sld_fab.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225406175 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225406175 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab " "Found entity 1: alt_sld_fab_alt_sld_fab" {  } { { "db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab.v" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225406279 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225406279 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_ident.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_ident.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_ident " "Found entity 1: alt_sld_fab_alt_sld_fab_ident" {  } { { "db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_ident.sv" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_ident.sv" 33 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225406297 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225406297 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_presplit.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_presplit " "Found entity 1: alt_sld_fab_alt_sld_fab_presplit" {  } { { "db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225406373 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225406373 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric-rtl " "Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl" {  } { { "db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 102 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225406479 ""} { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric " "Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric" {  } { { "db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 11 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225406479 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225406479 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_splitter.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_splitter " "Found entity 1: alt_sld_fab_alt_sld_fab_splitter" {  } { { "db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600225406568 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225406568 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "quotient\[20\] GND " "Pin \"quotient\[20\]\" is stuck at GND" {  } { { "fs20_01.bdf" "" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { { 360 760 936 376 "quotient\[20..0\]" "" } { 192 328 440 209 "quotient\[10..0\]" "" } { 352 648 760 369 "quotient\[20..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600225414675 "|fs20_01|quotient[20]"} { "Warning" "WMLS_MLS_STUCK_PIN" "quotient\[19\] GND " "Pin \"quotient\[19\]\" is stuck at GND" {  } { { "fs20_01.bdf" "" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { { 360 760 936 376 "quotient\[20..0\]" "" } { 192 328 440 209 "quotient\[10..0\]" "" } { 352 648 760 369 "quotient\[20..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600225414675 "|fs20_01|quotient[19]"} { "Warning" "WMLS_MLS_STUCK_PIN" "quotient\[18\] GND " "Pin \"quotient\[18\]\" is stuck at GND" {  } { { "fs20_01.bdf" "" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { { 360 760 936 376 "quotient\[20..0\]" "" } { 192 328 440 209 "quotient\[10..0\]" "" } { 352 648 760 369 "quotient\[20..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600225414675 "|fs20_01|quotient[18]"} { "Warning" "WMLS_MLS_STUCK_PIN" "test1\[20\] GND " "Pin \"test1\[20\]\" is stuck at GND" {  } { { "fs20_01.bdf" "" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { { 560 752 928 576 "test1\[20..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600225414675 "|fs20_01|test1[20]"} { "Warning" "WMLS_MLS_STUCK_PIN" "test1\[19\] GND " "Pin \"test1\[19\]\" is stuck at GND" {  } { { "fs20_01.bdf" "" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { { 560 752 928 576 "test1\[20..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600225414675 "|fs20_01|test1[19]"} { "Warning" "WMLS_MLS_STUCK_PIN" "test1\[18\] GND " "Pin \"test1\[18\]\" is stuck at GND" {  } { { "fs20_01.bdf" "" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { { 560 752 928 576 "test1\[20..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600225414675 "|fs20_01|test1[18]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1600225414675 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225414803 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "8 " "8 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1600225415624 ""}
{ "Info" "IAMERGE_SLD_INSTANCE_WITH_FULL_CONNECTIONS" "auto_signaltap_0 211 " "Successfully connected in-system debug instance \"auto_signaltap_0\" to all 211 required data inputs, trigger inputs, acquisition clocks, and dynamic pins" {  } {  } 0 35024 "Successfully connected in-system debug instance \"%1!s!\" to all %2!d! required data inputs, trigger inputs, acquisition clocks, and dynamic pins" 0 0 "Analysis & Synthesis" 0 -1 1600225419479 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1600225419650 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600225419650 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2839 " "Implemented 2839 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1600225420584 ""} { "Info" "ICUT_CUT_TM_OPINS" "44 " "Implemented 44 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1600225420584 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2700 " "Implemented 2700 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1600225420584 ""} { "Info" "ICUT_CUT_TM_RAMS" "89 " "Implemented 89 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1600225420584 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1600225420584 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1600225420584 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4883 " "Peak virtual memory: 4883 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600225420955 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 11:03:40 2020 " "Processing ended: Wed Sep 16 11:03:40 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600225420955 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:10 " "Elapsed time: 00:01:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600225420955 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:39 " "Total CPU time (on all processors): 00:01:39" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600225420955 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1600225420955 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1600225423751 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1600225423798 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 11:03:42 2020 " "Processing started: Wed Sep 16 11:03:42 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1600225423798 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1600225423798 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off fs20_01 -c fs20_01 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off fs20_01 -c fs20_01" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1600225423798 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1600225424228 ""}
{ "Info" "0" "" "Project  = fs20_01" {  } {  } 0 0 "Project  = fs20_01" 0 0 "Fitter" 0 0 1600225424228 ""}
{ "Info" "0" "" "Revision = fs20_01" {  } {  } 0 0 "Revision = fs20_01" 0 0 "Fitter" 0 0 1600225424229 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1600225424672 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1600225424675 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "fs20_01 10M08SCM153I7G " "Selected device 10M08SCM153I7G for design \"fs20_01\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1600225424812 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600225424905 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600225424905 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "alt_pll_220_110:a_pll_220_110\|altpll:altpll_component\|alt_pll_220_110_altpll:auto_generated\|pll1 MAX 10 PLL " "Implemented PLL \"alt_pll_220_110:a_pll_220_110\|altpll:altpll_component\|alt_pll_220_110_altpll:auto_generated\|pll1\" as MAX 10 PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "alt_pll_220_110:a_pll_220_110\|altpll:altpll_component\|alt_pll_220_110_altpll:auto_generated\|wire_pll1_clk\[0\] 6 1 0 0 " "Implementing clock multiplication of 6, clock division of 1, and phase shift of 0 degrees (0 ps) for alt_pll_220_110:a_pll_220_110\|altpll:altpll_component\|alt_pll_220_110_altpll:auto_generated\|wire_pll1_clk\[0\] port" {  } { { "db/alt_pll_220_110_altpll.v" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_pll_220_110_altpll.v" 46 -1 0 } } { "" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 1122 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1600225425016 ""}  } { { "db/alt_pll_220_110_altpll.v" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_pll_220_110_altpll.v" 46 -1 0 } } { "" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 1122 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1600225425016 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1600225425175 ""}
{ "Critical Warning" "WFCUDA_FCUDA_SPS_DEVICE_POWER_LIMITATION" "" "Review the PowerPlay Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." {  } {  } 1 16562 "Review the PowerPlay Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." 0 0 "Fitter" 0 -1 1600225425480 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M04SCM153I7G " "Device 10M04SCM153I7G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1600225425514 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M02SCM153I7G " "Device 10M02SCM153I7G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1600225425514 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1600225425514 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ D8 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8" {  } { { "d:/intelfpga/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 8354 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1600225425575 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ E8 " "Pin ~ALTERA_nCONFIG~ is reserved at location E8" {  } { { "d:/intelfpga/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 8356 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1600225425575 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ D6 " "Pin ~ALTERA_nSTATUS~ is reserved at location D6" {  } { { "d:/intelfpga/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 8358 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1600225425575 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ E6 " "Pin ~ALTERA_CONF_DONE~ is reserved at location E6" {  } { { "d:/intelfpga/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 8360 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1600225425575 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1600225425575 ""}
{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" {  } {  } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1600225425577 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1600225425577 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1600225425577 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1600225425577 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1600225425588 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1600225425721 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "37 44 " "No exact pin location assignment(s) for 37 pins of 44 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1600225426078 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1600225427745 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1600225427745 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1600225427745 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1600225427745 ""}
{ "Info" "ISTA_SDC_FOUND" "SDC1.sdc " "Reading SDC File: 'SDC1.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1600225427773 ""}
{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" {  } {  } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "Fitter" 0 -1 1600225427775 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 6 -duty_cycle 50.00 -name \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 6 -duty_cycle 50.00 -name \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1600225427778 ""}  } {  } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1600225427778 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." {  } {  } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1600225427778 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1600225427798 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "Fitter" 0 -1 1600225427798 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1600225427828 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1600225427846 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1600225427852 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1600225427852 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  10.416 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\] " "  10.416 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1600225427852 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1600225427852 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  62.500    clk_input " "  62.500    clk_input" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1600225427852 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1600225427852 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "alt_pll_220_110:a_pll_220_110\|altpll:altpll_component\|alt_pll_220_110_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1) " "Automatically promoted node alt_pll_220_110:a_pll_220_110\|altpll:altpll_component\|alt_pll_220_110_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1600225428149 ""}  } { { "db/alt_pll_220_110_altpll.v" "" { Text "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_pll_220_110_altpll.v" 81 -1 0 } } { "temporary_test_loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 1122 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1600225428149 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1600225428149 ""}  } { { "temporary_test_loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 2532 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1600225428149 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|reset_all  " "Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|reset_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1600225428149 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[0\]~0 " "Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[0\]~0" {  } { { "sld_buffer_manager.vhd" "" { Text "d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 356 -1 0 } } { "temporary_test_loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 5572 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1600225428149 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~0 " "Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~0" {  } { { "sld_buffer_manager.vhd" "" { Text "d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 638 -1 0 } } { "temporary_test_loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 5596 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1600225428149 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" {  } { { "sld_buffer_manager.vhd" "" { Text "d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 638 -1 0 } } { "temporary_test_loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 3181 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1600225428149 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1600225428149 ""}  } { { "sld_signaltap_impl.vhd" "" { Text "d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd" 882 -1 0 } } { "temporary_test_loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 4295 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1600225428149 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1600225429090 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600225429099 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600225429100 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1600225429109 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1600225429121 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1600225429147 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1600225429147 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1600225429152 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1600225429518 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1600225429528 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1600225429528 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "37 unused 2.5V 0 37 0 " "Number of I/O pins in group: 37 (unused VREF, 2.5V VCCIO, 0 input, 37 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1600225429549 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1600225429549 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1600225429549 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 0 8 " "I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  8 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1600225429550 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1B does not use undetermined 4 6 " "I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  6 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1600225429550 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 2.5V 2 8 " "I/O bank number 2 does not use VREF pins and has 2.5V VCCIO pins. 2 total pin(s) used --  8 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1600225429550 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 2.5V 2 26 " "I/O bank number 3 does not use VREF pins and has 2.5V VCCIO pins. 2 total pin(s) used --  26 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1600225429550 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 12 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1600225429550 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 16 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  16 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1600225429550 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 2.5V 7 21 " "I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 7 total pin(s) used --  21 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1600225429550 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1600225429550 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1600225429550 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Fitter preparation operations ending: elapsed time is 00:00:04" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600225429776 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1600225429822 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1600225431959 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600225432966 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1600225433033 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1600225443864 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:11 " "Fitter placement operations ending: elapsed time is 00:00:11" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600225443864 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1600225445638 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "9 X10_Y0 X20_Y12 " "Router estimated peak interconnect usage is 9% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12" {  } { { "loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 1 { 0 "Router estimated peak interconnect usage is 9% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12"} { { 12 { 0 ""} 10 0 11 13 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1600225448046 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1600225448046 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1600225450338 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1600225450338 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600225450348 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 3.03 " "Total time spent on timing analysis during the Fitter is 3.03 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1600225451116 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1600225451197 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1600225453131 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1600225453133 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1600225455010 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:05 " "Fitter post-fit operations ending: elapsed time is 00:00:05" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600225456126 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 MAX 10 " "1 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk_in_16M 3.3-V LVCMOS K4 " "Pin clk_in_16M uses I/O standard 3.3-V LVCMOS at K4" {  } { { "d:/intelfpga/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/16.1/quartus/bin64/pin_planner.ppl" { clk_in_16M } } } { "d:/intelfpga/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk_in_16M" } } } } { "fs20_01.bdf" "" { Schematic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf" { { -72 32 200 -56 "clk_in_16M" "" } } } } { "temporary_test_loc" "" { Generic "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/" { { 0 { 0 ""} 0 103 14176 15139 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1600225456469 ""}  } {  } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1600225456469 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/output_files/fs20_01.fit.smsg " "Generated suppressed messages file E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/output_files/fs20_01.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1600225456802 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5359 " "Peak virtual memory: 5359 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600225460706 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 11:04:20 2020 " "Processing ended: Wed Sep 16 11:04:20 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600225460706 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Elapsed time: 00:00:38" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600225460706 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600225460706 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1600225460706 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1600225463242 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1600225463276 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 11:04:22 2020 " "Processing started: Wed Sep 16 11:04:22 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1600225463276 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1600225463276 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off fs20_01 -c fs20_01 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off fs20_01 -c fs20_01" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1600225463277 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1600225463896 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1600225465493 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1600225465576 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4700 " "Peak virtual memory: 4700 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600225466322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 11:04:26 2020 " "Processing ended: Wed Sep 16 11:04:26 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600225466322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600225466322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600225466322 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1600225466322 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1600225468011 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "PowerPlay Power Analyzer Quartus Prime " "Running Quartus Prime PowerPlay Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1600225468029 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 11:04:27 2020 " "Processing started: Wed Sep 16 11:04:27 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1600225468029 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225468029 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off fs20_01 -c fs20_01 " "Command: quartus_pow --read_settings_files=off --write_settings_files=off fs20_01 -c fs20_01" {  } {  } 0 0 "Command: %1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225468029 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "PowerPlay Power Analyzer" 0 -1 1600225468584 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225468602 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225468602 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1600225469434 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1600225469434 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1600225469434 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225469434 ""}
{ "Info" "ISTA_SDC_FOUND" "SDC1.sdc " "Reading SDC File: 'SDC1.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225469466 ""}
{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" {  } {  } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225469467 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 6 -duty_cycle 50.00 -name \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 6 -duty_cycle 50.00 -name \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1600225469469 ""}  } {  } 0 332110 "%1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225469469 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." {  } {  } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "PowerPlay Power Analyzer" 0 -1 1600225469470 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1600225469486 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "PowerPlay Power Analyzer" 0 -1 1600225469486 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225469505 ""}
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" {  } {  } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225469561 ""}
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" {  } {  } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225469649 ""}
{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" {  } {  } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225469992 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225470094 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225472101 ""}
{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "7.549 millions of transitions / sec " "Average toggle rate for this design is 7.549 millions of transitions / sec" {  } {  } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225473950 ""}
{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "228.25 mW " "Total thermal power estimate for the design is 228.25 mW" {  } { { "d:/intelfpga/16.1/quartus/bin64/Report_Window_01.qrpt" "" { Report "d:/intelfpga/16.1/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } }  } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225474099 ""}
{ "Info" "IQEXE_ERROR_COUNT" "PowerPlay Power Analyzer 0 s 2 s Quartus Prime " "Quartus Prime PowerPlay Power Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4817 " "Peak virtual memory: 4817 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600225474487 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 11:04:34 2020 " "Processing ended: Wed Sep 16 11:04:34 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600225474487 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600225474487 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600225474487 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225474487 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "PowerPlay Power Analyzer" 0 -1 1600225476659 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1600225476688 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 11:04:35 2020 " "Processing started: Wed Sep 16 11:04:35 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1600225476688 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225476688 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta fs20_01 -c fs20_01 " "Command: quartus_sta fs20_01 -c fs20_01" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225476688 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1600225477025 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225477436 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225477436 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225477478 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225477478 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1600225477879 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1600225477879 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1600225477879 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225477879 ""}
{ "Info" "ISTA_SDC_FOUND" "SDC1.sdc " "Reading SDC File: 'SDC1.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225477932 ""}
{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" {  } {  } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225477936 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 6 -duty_cycle 50.00 -name \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 6 -duty_cycle 50.00 -name \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1600225477938 ""}  } {  } 0 332110 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225477938 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." {  } {  } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225477941 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1600225477994 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225477994 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225478011 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1600225478014 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 100C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 100C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1600225478085 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1600225478161 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225478191 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.427 " "Worst-case setup slack is -47.427" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478214 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478214 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -47.427           -1352.004 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "  -47.427           -1352.004 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478214 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   44.032               0.000 altera_reserved_tck  " "   44.032               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478214 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225478214 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.248 " "Worst-case hold slack is 0.248" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478259 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478259 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.248               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.248               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478259 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.348               0.000 altera_reserved_tck  " "    0.348               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478259 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225478259 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 95.952 " "Worst-case recovery slack is 95.952" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478288 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478288 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   95.952               0.000 altera_reserved_tck  " "   95.952               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478288 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225478288 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.920 " "Worst-case removal slack is 0.920" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478319 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478319 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.920               0.000 altera_reserved_tck  " "    0.920               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478319 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225478319 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.866 " "Worst-case minimum pulse width slack is 4.866" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.866               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    4.866               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   31.062               0.000 clk_input  " "   31.062               0.000 clk_input " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.517               0.000 altera_reserved_tck  " "   49.517               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225478346 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225478346 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225478407 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225478407 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 4 Registers " "Shortest Synchronizer Chain: 4 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225478407 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225478407 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 341.233 ns " "Worst Case Available Settling Time: 341.233 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225478407 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225478407 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225478407 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV -40C Model" {  } {  } 0 0 "Analyzing Slow 1200mV -40C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1600225478437 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225478519 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481101 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1600225481349 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481349 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481350 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481415 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -39.296 " "Worst-case setup slack is -39.296" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481431 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481431 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -39.296           -1045.319 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "  -39.296           -1045.319 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481431 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   44.683               0.000 altera_reserved_tck  " "   44.683               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481431 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481431 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.240 " "Worst-case hold slack is 0.240" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481469 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481469 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.240               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.240               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481469 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.298               0.000 altera_reserved_tck  " "    0.298               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481469 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481469 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 96.477 " "Worst-case recovery slack is 96.477" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   96.477               0.000 altera_reserved_tck  " "   96.477               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481492 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481492 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.817 " "Worst-case removal slack is 0.817" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481510 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481510 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.817               0.000 altera_reserved_tck  " "    0.817               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481510 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481510 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.870 " "Worst-case minimum pulse width slack is 4.870" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.870               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    4.870               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   31.094               0.000 clk_input  " "   31.094               0.000 clk_input " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.539               0.000 altera_reserved_tck  " "   49.539               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481532 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481532 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225481561 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225481561 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 4 Registers " "Shortest Synchronizer Chain: 4 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225481561 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225481561 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 342.276 ns " "Worst Case Available Settling Time: 342.276 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225481561 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225481561 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481561 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV -40C Model" {  } {  } 0 0 "Analyzing Fast 1200mV -40C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1600225481583 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1600225481835 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481835 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481836 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481854 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -11.481 " "Worst-case setup slack is -11.481" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481871 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481871 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -11.481            -147.200 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "  -11.481            -147.200 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481871 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   47.737               0.000 altera_reserved_tck  " "   47.737               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481871 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481871 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.093 " "Worst-case hold slack is 0.093" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481908 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481908 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.093               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.093               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481908 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.144               0.000 altera_reserved_tck  " "    0.144               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481908 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481908 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 98.077 " "Worst-case recovery slack is 98.077" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   98.077               0.000 altera_reserved_tck  " "   98.077               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481928 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481928 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.393 " "Worst-case removal slack is 0.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481949 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481949 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.393               0.000 altera_reserved_tck  " "    0.393               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481949 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481949 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.928 " "Worst-case minimum pulse width slack is 4.928" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481969 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481969 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.928               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    4.928               0.000 a_pll_220_110\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481969 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   30.758               0.000 clk_input  " "   30.758               0.000 clk_input " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481969 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.396               0.000 altera_reserved_tck  " "   49.396               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600225481969 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225481969 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225482002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225482002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 4 Registers " "Shortest Synchronizer Chain: 4 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225482002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225482002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 346.564 ns " "Worst Case Available Settling Time: 346.564 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225482002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1600225482002 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225482002 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225483686 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225483693 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4791 " "Peak virtual memory: 4791 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600225484116 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 11:04:44 2020 " "Processing ended: Wed Sep 16 11:04:44 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600225484116 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600225484116 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600225484116 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225484116 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600225486355 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1600225486390 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 11:04:45 2020 " "Processing started: Wed Sep 16 11:04:45 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1600225486390 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1600225486390 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off fs20_01 -c fs20_01 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off fs20_01 -c fs20_01" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1600225486390 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1600225487988 ""}
{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." {  } {  } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1600225488735 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "fs20_01.vo E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/simulation/modelsim/ simulation " "Generated file fs20_01.vo in folder \"E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1600225495055 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4696 " "Peak virtual memory: 4696 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600225496672 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 11:04:56 2020 " "Processing ended: Wed Sep 16 11:04:56 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600225496672 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600225496672 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600225496672 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1600225496672 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 31 s " "Quartus Prime Full Compilation was successful. 0 errors, 31 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1600225497618 ""}
