Analysis & Synthesis report for fs20_01
Wed Sep 16 13:23:24 2020
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. State Machine - |fs20_01|test_div_1:inst|S_state_reg
 11. Registers Removed During Synthesis
 12. Removed Registers Triggering Further Register Optimizations
 13. General Register Statistics
 14. Inverted Register Statistics
 15. Multiplexer Restructuring Statistics (Restructuring Performed)
 16. Source assignments for inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider
 17. Source assignments for sld_signaltap:auto_signaltap_0
 18. Parameter Settings for User Entity Instance: alt_pll_220_110:a_pll_220_110|altpll:altpll_component
 19. Parameter Settings for User Entity Instance: inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component
 20. Parameter Settings for User Entity Instance: div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component
 21. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 22. altpll Parameter Settings by Entity Instance
 23. SignalTap II Logic Analyzer Settings
 24. Post-Synthesis Netlist Statistics for Top Partition
 25. Elapsed Time Per Partition
 26. Connections to In-System Debugging Instance "auto_signaltap_0"
 27. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2016  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
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to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Intel and sold by Intel or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+--------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                         ;
+------------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Wed Sep 16 13:23:24 2020           ;
; Quartus Prime Version              ; 16.1.0 Build 196 10/24/2016 SJ Standard Edition ;
; Revision Name                      ; fs20_01                                         ;
; Top-level Entity Name              ; fs20_01                                         ;
; Family                             ; MAX 10                                          ;
; Total logic elements               ; 2,628                                           ;
;     Total combinational functions  ; 1,592                                           ;
;     Dedicated logic registers      ; 1,609                                           ;
; Total registers                    ; 1609                                            ;
; Total pins                         ; 44                                              ;
; Total virtual pins                 ; 0                                               ;
; Total memory bits                  ; 182,272                                         ;
; Embedded Multiplier 9-bit elements ; 0                                               ;
; Total PLLs                         ; 1                                               ;
; UFM blocks                         ; 0                                               ;
; ADC blocks                         ; 0                                               ;
+------------------------------------+-------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; 10M08SCM153I7G     ;                    ;
; Top-level entity name                                                      ; fs20_01            ; fs20_01            ;
; Family name                                                                ; MAX 10             ; Cyclone V          ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; OpenCore Plus hardware evaluation                                          ; Enable             ; Enable             ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                                                                         ;
+--------------------------------------------------------------------+-----------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------+
; File Name with User-Entered Path                                   ; Used in Netlist ; File Type                                    ; File Name with Absolute Path                                                                                               ; Library     ;
+--------------------------------------------------------------------+-----------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------+
; fs20_01.bdf                                                        ; yes             ; User Block Diagram/Schematic File            ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/fs20_01.bdf                                                        ;             ;
; alt_pll_220_110.vhd                                                ; yes             ; User Wizard-Generated File                   ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/alt_pll_220_110.vhd                                                ;             ;
; div_no_pipeline.vhd                                                ; yes             ; User Wizard-Generated File                   ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/div_no_pipeline.vhd                                                ;             ;
; inc_div_test.vhd                                                   ; yes             ; User Wizard-Generated File                   ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/inc_div_test.vhd                                                   ;             ;
; test_div_1.vhd                                                     ; yes             ; User VHDL File                               ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/test_div_1.vhd                                                     ;             ;
; altpll.tdf                                                         ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/altpll.tdf                                                               ;             ;
; aglobal161.inc                                                     ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/aglobal161.inc                                                           ;             ;
; stratix_pll.inc                                                    ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/stratix_pll.inc                                                          ;             ;
; stratixii_pll.inc                                                  ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/stratixii_pll.inc                                                        ;             ;
; cycloneii_pll.inc                                                  ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/cycloneii_pll.inc                                                        ;             ;
; db/alt_pll_220_110_altpll.v                                        ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_pll_220_110_altpll.v                                        ;             ;
; lpm_divide.tdf                                                     ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_divide.tdf                                                           ;             ;
; abs_divider.inc                                                    ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/abs_divider.inc                                                          ;             ;
; sign_div_unsign.inc                                                ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sign_div_unsign.inc                                                      ;             ;
; db/lpm_divide_uft.tdf                                              ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/lpm_divide_uft.tdf                                              ;             ;
; db/sign_div_unsign_0qi.tdf                                         ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/sign_div_unsign_0qi.tdf                                         ;             ;
; db/alt_u_div_eqf.tdf                                               ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_u_div_eqf.tdf                                               ;             ;
; db/add_sub_t3c.tdf                                                 ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/add_sub_t3c.tdf                                                 ;             ;
; db/add_sub_u3c.tdf                                                 ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/add_sub_u3c.tdf                                                 ;             ;
; db/lpm_divide_p0r.tdf                                              ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/lpm_divide_p0r.tdf                                              ;             ;
; db/sign_div_unsign_6nh.tdf                                         ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/sign_div_unsign_6nh.tdf                                         ;             ;
; db/alt_u_div_lke.tdf                                               ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_u_div_lke.tdf                                               ;             ;
; sld_signaltap.vhd                                                  ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_signaltap.vhd                                                        ;             ;
; sld_signaltap_impl.vhd                                             ; yes             ; Encrypted Megafunction                       ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd                                                   ;             ;
; sld_ela_control.vhd                                                ; yes             ; Encrypted Megafunction                       ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_ela_control.vhd                                                      ;             ;
; lpm_shiftreg.tdf                                                   ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_shiftreg.tdf                                                         ;             ;
; lpm_constant.inc                                                   ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_constant.inc                                                         ;             ;
; dffeea.inc                                                         ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/dffeea.inc                                                               ;             ;
; sld_mbpmg.vhd                                                      ; yes             ; Encrypted Megafunction                       ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_mbpmg.vhd                                                            ;             ;
; sld_ela_trigger_flow_mgr.vhd                                       ; yes             ; Encrypted Megafunction                       ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd                                             ;             ;
; sld_buffer_manager.vhd                                             ; yes             ; Encrypted Megafunction                       ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd                                                   ;             ;
; altsyncram.tdf                                                     ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/altsyncram.tdf                                                           ;             ;
; stratix_ram_block.inc                                              ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/stratix_ram_block.inc                                                    ;             ;
; lpm_mux.inc                                                        ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_mux.inc                                                              ;             ;
; lpm_decode.inc                                                     ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_decode.inc                                                           ;             ;
; a_rdenreg.inc                                                      ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/a_rdenreg.inc                                                            ;             ;
; altrom.inc                                                         ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/altrom.inc                                                               ;             ;
; altram.inc                                                         ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/altram.inc                                                               ;             ;
; altdpram.inc                                                       ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/altdpram.inc                                                             ;             ;
; db/altsyncram_am14.tdf                                             ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/altsyncram_am14.tdf                                             ;             ;
; altdpram.tdf                                                       ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/altdpram.tdf                                                             ;             ;
; memmodes.inc                                                       ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/others/maxplus2/memmodes.inc                                                           ;             ;
; a_hdffe.inc                                                        ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/a_hdffe.inc                                                              ;             ;
; alt_le_rden_reg.inc                                                ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/alt_le_rden_reg.inc                                                      ;             ;
; altsyncram.inc                                                     ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/altsyncram.inc                                                           ;             ;
; lpm_mux.tdf                                                        ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_mux.tdf                                                              ;             ;
; muxlut.inc                                                         ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/muxlut.inc                                                               ;             ;
; bypassff.inc                                                       ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/bypassff.inc                                                             ;             ;
; altshift.inc                                                       ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/altshift.inc                                                             ;             ;
; db/mux_h7c.tdf                                                     ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/mux_h7c.tdf                                                     ;             ;
; lpm_decode.tdf                                                     ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_decode.tdf                                                           ;             ;
; declut.inc                                                         ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/declut.inc                                                               ;             ;
; lpm_compare.inc                                                    ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_compare.inc                                                          ;             ;
; db/decode_3af.tdf                                                  ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/decode_3af.tdf                                                  ;             ;
; lpm_counter.tdf                                                    ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_counter.tdf                                                          ;             ;
; lpm_add_sub.inc                                                    ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_add_sub.inc                                                          ;             ;
; cmpconst.inc                                                       ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/cmpconst.inc                                                             ;             ;
; lpm_counter.inc                                                    ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_counter.inc                                                          ;             ;
; alt_counter_stratix.inc                                            ; yes             ; Megafunction                                 ; d:/intelfpga/16.1/quartus/libraries/megafunctions/alt_counter_stratix.inc                                                  ;             ;
; db/cntr_lrh.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_lrh.tdf                                                    ;             ;
; db/cmpr_jrb.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cmpr_jrb.tdf                                                    ;             ;
; db/cntr_6ki.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_6ki.tdf                                                    ;             ;
; db/cntr_4rh.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_4rh.tdf                                                    ;             ;
; db/cmpr_hrb.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cmpr_hrb.tdf                                                    ;             ;
; db/cntr_odi.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_odi.tdf                                                    ;             ;
; db/cmpr_drb.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cmpr_drb.tdf                                                    ;             ;
; sld_rom_sr.vhd                                                     ; yes             ; Encrypted Megafunction                       ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_rom_sr.vhd                                                           ;             ;
; sld_jtag_endpoint_adapter.vhd                                      ; yes             ; Encrypted Megafunction                       ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd                                            ;             ;
; sld_jtag_endpoint_adapter_impl.sv                                  ; yes             ; Encrypted Megafunction                       ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter_impl.sv                                        ;             ;
; sld_hub.vhd                                                        ; yes             ; Encrypted Megafunction                       ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_hub.vhd                                                              ; altera_sld  ;
; db/ip/sld5df68646/alt_sld_fab.v                                    ; yes             ; Encrypted Auto-Found Verilog HDL File        ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/alt_sld_fab.v                                    ; alt_sld_fab ;
; db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab.v             ; yes             ; Encrypted Auto-Found Verilog HDL File        ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab.v             ; alt_sld_fab ;
; db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_ident.sv      ; yes             ; Auto-Found SystemVerilog HDL File            ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_ident.sv      ; alt_sld_fab ;
; db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_presplit.sv   ; yes             ; Encrypted Auto-Found SystemVerilog HDL File  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_presplit.sv   ; alt_sld_fab ;
; db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd ; yes             ; Encrypted Auto-Found VHDL File               ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd ; alt_sld_fab ;
; db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_splitter.sv   ; yes             ; Encrypted Auto-Found SystemVerilog HDL File  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_splitter.sv   ; alt_sld_fab ;
; sld_jtag_hub.vhd                                                   ; yes             ; Encrypted Megafunction                       ; d:/intelfpga/16.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd                                                         ;             ;
; db/lpm_divide_osr.tdf                                              ; yes             ; Auto-Generated Megafunction                  ; E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/lpm_divide_osr.tdf                                              ;             ;
+--------------------------------------------------------------------+-----------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                                                ;
+---------------------------------------------+--------------------------------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                                        ;
+---------------------------------------------+--------------------------------------------------------------------------------------------------------------+
; Estimated Total logic elements              ; 2,628                                                                                                        ;
;                                             ;                                                                                                              ;
; Total combinational functions               ; 1592                                                                                                         ;
; Logic element usage by number of LUT inputs ;                                                                                                              ;
;     -- 4 input functions                    ; 480                                                                                                          ;
;     -- 3 input functions                    ; 738                                                                                                          ;
;     -- <=2 input functions                  ; 374                                                                                                          ;
;                                             ;                                                                                                              ;
; Logic elements by mode                      ;                                                                                                              ;
;     -- normal mode                          ; 1113                                                                                                         ;
;     -- arithmetic mode                      ; 479                                                                                                          ;
;                                             ;                                                                                                              ;
; Total registers                             ; 1609                                                                                                         ;
;     -- Dedicated logic registers            ; 1609                                                                                                         ;
;     -- I/O registers                        ; 0                                                                                                            ;
;                                             ;                                                                                                              ;
; I/O pins                                    ; 44                                                                                                           ;
; Total memory bits                           ; 182272                                                                                                       ;
;                                             ;                                                                                                              ;
; Embedded Multiplier 9-bit elements          ; 0                                                                                                            ;
;                                             ;                                                                                                              ;
; Total PLLs                                  ; 1                                                                                                            ;
;     -- PLLs                                 ; 1                                                                                                            ;
;                                             ;                                                                                                              ;
; Maximum fan-out node                        ; alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated|wire_pll1_clk[0] ;
; Maximum fan-out                             ; 1045                                                                                                         ;
; Total fan-out                               ; 11850                                                                                                        ;
; Average fan-out                             ; 3.50                                                                                                         ;
+---------------------------------------------+--------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
; Compilation Hierarchy Node                                                                                                              ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name                                                                                                                                                                                                                                                                                                                                 ; Entity Name                       ; Library Name ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
; |fs20_01                                                                                                                                ; 1592 (2)            ; 1609 (0)                  ; 182272      ; 0          ; 0            ; 0       ; 0         ; 44   ; 0            ; 0          ; |fs20_01                                                                                                                                                                                                                                                                                                                                            ; fs20_01                           ; work         ;
;    |alt_pll_220_110:a_pll_220_110|                                                                                                      ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|alt_pll_220_110:a_pll_220_110                                                                                                                                                                                                                                                                                                              ; alt_pll_220_110                   ; work         ;
;       |altpll:altpll_component|                                                                                                         ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|alt_pll_220_110:a_pll_220_110|altpll:altpll_component                                                                                                                                                                                                                                                                                      ; altpll                            ; work         ;
;          |alt_pll_220_110_altpll:auto_generated|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated                                                                                                                                                                                                                                                ; alt_pll_220_110_altpll            ; work         ;
;    |div_no_pipeline:no_pipeline|                                                                                                        ; 401 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|div_no_pipeline:no_pipeline                                                                                                                                                                                                                                                                                                                ; div_no_pipeline                   ; work         ;
;       |lpm_divide:LPM_DIVIDE_component|                                                                                                 ; 401 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component                                                                                                                                                                                                                                                                                ; lpm_divide                        ; work         ;
;          |lpm_divide_p0r:auto_generated|                                                                                                ; 401 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated                                                                                                                                                                                                                                                  ; lpm_divide_p0r                    ; work         ;
;             |sign_div_unsign_6nh:divider|                                                                                               ; 401 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider                                                                                                                                                                                                                      ; sign_div_unsign_6nh               ; work         ;
;                |alt_u_div_lke:divider|                                                                                                  ; 401 (401)           ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider                                                                                                                                                                                                ; alt_u_div_lke                     ; work         ;
;    |inc_div_test:inst1|                                                                                                                 ; 361 (0)             ; 56 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|inc_div_test:inst1                                                                                                                                                                                                                                                                                                                         ; inc_div_test                      ; work         ;
;       |lpm_divide:LPM_DIVIDE_component|                                                                                                 ; 361 (0)             ; 56 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component                                                                                                                                                                                                                                                                                         ; lpm_divide                        ; work         ;
;          |lpm_divide_uft:auto_generated|                                                                                                ; 361 (0)             ; 56 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated                                                                                                                                                                                                                                                           ; lpm_divide_uft                    ; work         ;
;             |sign_div_unsign_0qi:divider|                                                                                               ; 361 (0)             ; 56 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider                                                                                                                                                                                                                               ; sign_div_unsign_0qi               ; work         ;
;                |alt_u_div_eqf:divider|                                                                                                  ; 361 (361)           ; 56 (56)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider                                                                                                                                                                                                         ; alt_u_div_eqf                     ; work         ;
;    |sld_hub:auto_hub|                                                                                                                   ; 128 (1)             ; 91 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_hub:auto_hub                                                                                                                                                                                                                                                                                                                           ; sld_hub                           ; altera_sld   ;
;       |alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric| ; 127 (0)             ; 91 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric                                                                                                                                                                                           ; alt_sld_fab_with_jtag_input       ; altera_sld   ;
;          |alt_sld_fab:instrumentation_fabric|                                                                                           ; 127 (0)             ; 91 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric                                                                                                                                                        ; alt_sld_fab                       ; alt_sld_fab  ;
;             |alt_sld_fab_alt_sld_fab:alt_sld_fab|                                                                                       ; 127 (1)             ; 91 (5)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab                                                                                                                    ; alt_sld_fab_alt_sld_fab           ; alt_sld_fab  ;
;                |alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|                                                                            ; 126 (0)             ; 86 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric                                                                        ; alt_sld_fab_alt_sld_fab_sldfabric ; alt_sld_fab  ;
;                   |sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|                                                                        ; 126 (87)            ; 86 (58)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub                           ; sld_jtag_hub                      ; work         ;
;                      |sld_rom_sr:hub_info_reg|                                                                                          ; 21 (21)             ; 9 (9)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg   ; sld_rom_sr                        ; work         ;
;                      |sld_shadow_jsm:shadow_jsm|                                                                                        ; 18 (18)             ; 19 (19)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm ; sld_shadow_jsm                    ; altera_sld   ;
;    |sld_signaltap:auto_signaltap_0|                                                                                                     ; 650 (2)             ; 1419 (178)                ; 182272      ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                                                                                                             ; sld_signaltap                     ; work         ;
;       |sld_signaltap_impl:sld_signaltap_body|                                                                                           ; 648 (0)             ; 1241 (0)                  ; 182272      ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body                                                                                                                                                                                                                                                                       ; sld_signaltap_impl                ; work         ;
;          |sld_signaltap_implb:sld_signaltap_body|                                                                                       ; 648 (88)            ; 1241 (438)                ; 182272      ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body                                                                                                                                                                                                                                ; sld_signaltap_implb               ; work         ;
;             |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|                                                            ; 25 (0)              ; 70 (70)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem                                                                                                                                                                 ; altdpram                          ; work         ;
;                |lpm_decode:wdecoder|                                                                                                    ; 2 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder                                                                                                                                             ; lpm_decode                        ; work         ;
;                   |decode_3af:auto_generated|                                                                                           ; 2 (2)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_3af:auto_generated                                                                                                                   ; decode_3af                        ; work         ;
;                |lpm_mux:mux|                                                                                                            ; 23 (0)              ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux                                                                                                                                                     ; lpm_mux                           ; work         ;
;                   |mux_h7c:auto_generated|                                                                                              ; 23 (23)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_h7c:auto_generated                                                                                                                              ; mux_h7c                           ; work         ;
;             |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|                                                                           ; 0 (0)               ; 0 (0)                     ; 182272      ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram                                                                                                                                                                                ; altsyncram                        ; work         ;
;                |altsyncram_am14:auto_generated|                                                                                         ; 0 (0)               ; 0 (0)                     ; 182272      ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated                                                                                                                                                 ; altsyncram_am14                   ; work         ;
;             |lpm_shiftreg:segment_offset_config_deserialize|                                                                            ; 0 (0)               ; 11 (11)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize                                                                                                                                                                                 ; lpm_shiftreg                      ; work         ;
;             |lpm_shiftreg:status_register|                                                                                              ; 17 (17)             ; 17 (17)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:status_register                                                                                                                                                                                                   ; lpm_shiftreg                      ; work         ;
;             |serial_crc_16:\tdo_crc_gen:tdo_crc_calc|                                                                                   ; 14 (14)             ; 13 (13)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc                                                                                                                                                                                        ; serial_crc_16                     ; work         ;
;             |sld_buffer_manager:sld_buffer_manager_inst|                                                                                ; 87 (87)             ; 64 (64)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst                                                                                                                                                                                     ; sld_buffer_manager                ; work         ;
;             |sld_ela_control:ela_control|                                                                                               ; 210 (1)             ; 461 (1)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control                                                                                                                                                                                                    ; sld_ela_control                   ; work         ;
;                |lpm_shiftreg:trigger_config_deserialize|                                                                                ; 0 (0)               ; 4 (4)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize                                                                                                                                                            ; lpm_shiftreg                      ; work         ;
;                |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|                                 ; 178 (0)             ; 445 (0)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm                                                                                                             ; sld_ela_basic_multi_level_trigger ; work         ;
;                   |lpm_shiftreg:trigger_condition_deserialize|                                                                          ; 0 (0)               ; 267 (267)                 ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize                                                                  ; lpm_shiftreg                      ; work         ;
;                   |sld_mbpmg:\trigger_modules_gen:0:trigger_match|                                                                      ; 178 (0)             ; 178 (0)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match                                                              ; sld_mbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:80:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:80:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:81:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:81:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:82:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:82:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:83:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:83:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:84:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:84:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:85:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:85:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:86:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:86:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:87:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:87:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:88:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:88:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1        ; sld_sbpmg                         ; work         ;
;                |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|                                                          ; 31 (31)             ; 11 (1)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity                                                                                                                                      ; sld_ela_trigger_flow_mgr          ; work         ;
;                   |lpm_shiftreg:trigger_config_deserialize|                                                                             ; 0 (0)               ; 10 (10)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize                                                                                              ; lpm_shiftreg                      ; work         ;
;             |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|                                          ; 177 (12)            ; 159 (0)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst                                                                                                                                               ; sld_offload_buffer_mgr            ; work         ;
;                |lpm_counter:\adv_point_3_and_more:advance_pointer_counter|                                                              ; 9 (0)               ; 7 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter                                                                                     ; lpm_counter                       ; work         ;
;                   |cntr_lrh:auto_generated|                                                                                             ; 9 (9)               ; 7 (7)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_lrh:auto_generated                                                             ; cntr_lrh                          ; work         ;
;                |lpm_counter:read_pointer_counter|                                                                                       ; 11 (0)              ; 11 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter                                                                                                              ; lpm_counter                       ; work         ;
;                   |cntr_6ki:auto_generated|                                                                                             ; 11 (11)             ; 11 (11)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_6ki:auto_generated                                                                                      ; cntr_6ki                          ; work         ;
;                |lpm_counter:status_advance_pointer_counter|                                                                             ; 7 (0)               ; 5 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter                                                                                                    ; lpm_counter                       ; work         ;
;                   |cntr_4rh:auto_generated|                                                                                             ; 7 (7)               ; 5 (5)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_4rh:auto_generated                                                                            ; cntr_4rh                          ; work         ;
;                |lpm_counter:status_read_pointer_counter|                                                                                ; 3 (0)               ; 1 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter                                                                                                       ; lpm_counter                       ; work         ;
;                   |cntr_odi:auto_generated|                                                                                             ; 3 (3)               ; 1 (1)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_odi:auto_generated                                                                               ; cntr_odi                          ; work         ;
;                |lpm_shiftreg:info_data_shift_out|                                                                                       ; 23 (23)             ; 23 (23)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out                                                                                                              ; lpm_shiftreg                      ; work         ;
;                |lpm_shiftreg:ram_data_shift_out|                                                                                        ; 89 (89)             ; 89 (89)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out                                                                                                               ; lpm_shiftreg                      ; work         ;
;                |lpm_shiftreg:status_data_shift_out|                                                                                     ; 23 (23)             ; 23 (23)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out                                                                                                            ; lpm_shiftreg                      ; work         ;
;             |sld_rom_sr:crc_rom_sr|                                                                                                     ; 30 (30)             ; 8 (8)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr                                                                                                                                                                                                          ; sld_rom_sr                        ; work         ;
;    |test_div_1:inst|                                                                                                                    ; 50 (50)             ; 43 (43)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |fs20_01|test_div_1:inst                                                                                                                                                                                                                                                                                                                            ; test_div_1                        ; work         ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                            ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; Name                                                                                                                                                                                                  ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF  ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_am14:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 2048         ; 89           ; 2048         ; 89           ; 182272 ; None ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                                                                                                                              ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                                                                                                                                                                                                                                                              ; IP Include File     ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+
; Altera ; ALTPLL       ; 16.1    ; N/A          ; N/A          ; |fs20_01|alt_pll_220_110:a_pll_220_110                                                                                                                                                                                                                                       ; alt_pll_220_110.vhd ;
; Altera ; Signal Tap   ; N/A     ; N/A          ; Licensed     ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric                                                                                 ;                     ;
; Altera ; Signal Tap   ; N/A     ; N/A          ; Licensed     ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab                                             ;                     ;
; Altera ; Signal Tap   ; N/A     ; N/A          ; Licensed     ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_presplit:presplit   ;                     ;
; Altera ; Signal Tap   ; N/A     ; N/A          ; Licensed     ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric ;                     ;
; Altera ; Signal Tap   ; N/A     ; N/A          ; Licensed     ; |fs20_01|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_splitter:splitter   ;                     ;
; Altera ; LPM_DIVIDE   ; 16.1    ; N/A          ; N/A          ; |fs20_01|inc_div_test:inst1                                                                                                                                                                                                                                                  ; inc_div_test.vhd    ;
; Altera ; LPM_DIVIDE   ; 16.1    ; N/A          ; N/A          ; |fs20_01|div_no_pipeline:no_pipeline                                                                                                                                                                                                                                         ; div_no_pipeline.vhd ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |fs20_01|test_div_1:inst|S_state_reg                                                                                                                                                                    ;
+------------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+------------------+
; Name             ; S_state_reg.st9 ; S_state_reg.st8 ; S_state_reg.st7 ; S_state_reg.st6 ; S_state_reg.st5 ; S_state_reg.st4 ; S_state_reg.st3 ; S_state_reg.st2 ; S_state_reg.st1 ; S_state_reg.st0 ; S_state_reg.idle ;
+------------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+------------------+
; S_state_reg.idle ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0                ;
; S_state_reg.st0  ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1               ; 1                ;
; S_state_reg.st1  ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1               ; 0               ; 1                ;
; S_state_reg.st2  ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1               ; 0               ; 0               ; 1                ;
; S_state_reg.st3  ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1               ; 0               ; 0               ; 0               ; 1                ;
; S_state_reg.st4  ; 0               ; 0               ; 0               ; 0               ; 0               ; 1               ; 0               ; 0               ; 0               ; 0               ; 1                ;
; S_state_reg.st5  ; 0               ; 0               ; 0               ; 0               ; 1               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1                ;
; S_state_reg.st6  ; 0               ; 0               ; 0               ; 1               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1                ;
; S_state_reg.st7  ; 0               ; 0               ; 1               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1                ;
; S_state_reg.st8  ; 0               ; 1               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1                ;
; S_state_reg.st9  ; 1               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1                ;
+------------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                  ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                   ; Reason for Removal                                                                                                                                                ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; test_div_1:inst|S_dividsor_reg[1,3]                                                                                                                             ; Stuck at VCC due to stuck port data_in                                                                                                                            ;
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[1,3]          ; Stuck at VCC due to stuck port data_in                                                                                                                            ;
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[18..20]          ; Stuck at GND due to stuck port data_in                                                                                                                            ;
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[13,15]        ; Stuck at VCC due to stuck port data_in                                                                                                                            ;
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[39..41]          ; Stuck at GND due to stuck port data_in                                                                                                                            ;
; test_div_1:inst|S_dividsor_reg[0]                                                                                                                               ; Merged with test_div_1:inst|S_dividsor_reg[2]                                                                                                                     ;
; test_div_1:inst|S_dividsor_reg[2]                                                                                                                               ; Merged with test_div_1:inst|S_dividsor_reg[4]                                                                                                                     ;
; test_div_1:inst|S_dividsor_reg[4]                                                                                                                               ; Merged with test_div_1:inst|S_dividsor_reg[5]                                                                                                                     ;
; test_div_1:inst|S_dividsor_reg[5]                                                                                                                               ; Merged with test_div_1:inst|S_dividsor_reg[6]                                                                                                                     ;
; test_div_1:inst|S_dividsor_reg[6]                                                                                                                               ; Merged with test_div_1:inst|S_dividsor_reg[7]                                                                                                                     ;
; test_div_1:inst|S_dividsor_reg[7]                                                                                                                               ; Merged with test_div_1:inst|S_dividsor_reg[8]                                                                                                                     ;
; test_div_1:inst|S_dividsor_reg[8]                                                                                                                               ; Merged with test_div_1:inst|S_dividsor_reg[9]                                                                                                                     ;
; test_div_1:inst|S_dividsor_reg[9]                                                                                                                               ; Merged with test_div_1:inst|S_dividsor_reg[10]                                                                                                                    ;
; test_div_1:inst|S_dividsor_reg[10]                                                                                                                              ; Merged with test_div_1:inst|S_dividsor_reg[11]                                                                                                                    ;
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[0,2,4..10]    ; Merged with inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[11] ;
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[12,14,16..22] ; Merged with inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[23] ;
; test_div_1:inst|S_state_reg.st2                                                                                                                                 ; Lost fanout                                                                                                                                                       ;
; test_div_1:inst|S_state_reg.st3                                                                                                                                 ; Lost fanout                                                                                                                                                       ;
; test_div_1:inst|S_state_reg.st4                                                                                                                                 ; Lost fanout                                                                                                                                                       ;
; test_div_1:inst|S_state_reg.st5                                                                                                                                 ; Lost fanout                                                                                                                                                       ;
; test_div_1:inst|S_state_reg.st6                                                                                                                                 ; Lost fanout                                                                                                                                                       ;
; test_div_1:inst|S_state_reg.st7                                                                                                                                 ; Lost fanout                                                                                                                                                       ;
; test_div_1:inst|S_state_reg.st8                                                                                                                                 ; Lost fanout                                                                                                                                                       ;
; test_div_1:inst|S_state_reg.st9                                                                                                                                 ; Lost fanout                                                                                                                                                       ;
; Total Number of Removed Registers = 47                                                                                                                          ;                                                                                                                                                                   ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                                                             ;
+----------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                      ; Reason for Removal        ; Registers Removed due to This Register                                                                                                                 ;
+----------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; test_div_1:inst|S_dividsor_reg[3]                                                                                                                  ; Stuck at VCC              ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[3],  ;
;                                                                                                                                                    ; due to stuck port data_in ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[20],    ;
;                                                                                                                                                    ;                           ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[15], ;
;                                                                                                                                                    ;                           ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[41]     ;
; test_div_1:inst|S_dividsor_reg[1]                                                                                                                  ; Stuck at VCC              ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[1],  ;
;                                                                                                                                                    ; due to stuck port data_in ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[13]  ;
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[19] ; Stuck at GND              ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[40]     ;
;                                                                                                                                                    ; due to stuck port data_in ;                                                                                                                                                        ;
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[18] ; Stuck at GND              ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[39]     ;
;                                                                                                                                                    ; due to stuck port data_in ;                                                                                                                                                        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1609  ;
; Number of registers using Synchronous Clear  ; 53    ;
; Number of registers using Synchronous Load   ; 81    ;
; Number of registers using Asynchronous Clear ; 521   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 681   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                                                                                                                                                                                               ; Fan out ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[23]                                                                                                                                                                           ; 50      ;
; test_div_1:inst|S_dividsor_reg[11]                                                                                                                                                                                                                                                                                              ; 214     ;
; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFDenominator[11]                                                                                                                                                                           ; 136     ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[2] ; 2       ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[1] ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[1]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[3]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[4]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[5]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[6]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[7]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[8]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[9]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[10]                                                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11]                                                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0]                                                                                                                                                   ; 1       ;
; Total number of inverted registers = 17                                                                                                                                                                                                                                                                                         ;         ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+
; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |fs20_01|test_div_1:inst|S_counter_reg[0] ;
; 4:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |fs20_01|test_div_1:inst|Selector9        ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |fs20_01|test_div_1:inst|Selector8        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider ;
+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                        ;
+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[0]                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[1]                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[2]                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[3]                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[4]                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[5]                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[6]                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[7]                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[8]                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[9]                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[10]                                                                                                           ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[11]                                                                                                           ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[12]                                                                                                           ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[13]                                                                                                           ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[14]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[15]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[16]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[17]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[18]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[19]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[20]                                                                                                           ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[21]                                                                                                           ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[22]                                                                                                           ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[23]                                                                                                           ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[24]                                                                                                           ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFQuotient[25]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[26]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[27]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[28]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[29]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[30]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[31]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[32]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[33]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[34]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[35]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[36]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[37]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[38]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[39]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[40]                                                                                                           ;
; POWER_UP_LEVEL ; LOW   ; -    ; DFFQuotient[41]                                                                                                           ;
; POWER_UP_LEVEL ; HIGH  ; -    ; DFFDenominator                                                                                                            ;
+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0 ;
+-----------------+-------+------+----------------------+
; Assignment      ; Value ; From ; To                   ;
+-----------------+-------+------+----------------------+
; MESSAGE_DISABLE ; 13410 ; -    ; -                    ;
+-----------------+-------+------+----------------------+


+----------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: alt_pll_220_110:a_pll_220_110|altpll:altpll_component ;
+-------------------------------+-----------------------------------+--------------------------------+
; Parameter Name                ; Value                             ; Type                           ;
+-------------------------------+-----------------------------------+--------------------------------+
; OPERATION_MODE                ; NORMAL                            ; Untyped                        ;
; PLL_TYPE                      ; AUTO                              ; Untyped                        ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=alt_pll_220_110 ; Untyped                        ;
; QUALIFY_CONF_DONE             ; OFF                               ; Untyped                        ;
; COMPENSATE_CLOCK              ; CLK0                              ; Untyped                        ;
; SCAN_CHAIN                    ; LONG                              ; Untyped                        ;
; PRIMARY_CLOCK                 ; INCLK0                            ; Untyped                        ;
; INCLK0_INPUT_FREQUENCY        ; 62500                             ; Signed Integer                 ;
; INCLK1_INPUT_FREQUENCY        ; 0                                 ; Untyped                        ;
; GATE_LOCK_SIGNAL              ; NO                                ; Untyped                        ;
; GATE_LOCK_COUNTER             ; 0                                 ; Untyped                        ;
; LOCK_HIGH                     ; 1                                 ; Untyped                        ;
; LOCK_LOW                      ; 1                                 ; Untyped                        ;
; VALID_LOCK_MULTIPLIER         ; 1                                 ; Untyped                        ;
; INVALID_LOCK_MULTIPLIER       ; 5                                 ; Untyped                        ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                               ; Untyped                        ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                               ; Untyped                        ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                               ; Untyped                        ;
; SKIP_VCO                      ; OFF                               ; Untyped                        ;
; SWITCH_OVER_COUNTER           ; 0                                 ; Untyped                        ;
; SWITCH_OVER_TYPE              ; AUTO                              ; Untyped                        ;
; FEEDBACK_SOURCE               ; EXTCLK0                           ; Untyped                        ;
; BANDWIDTH                     ; 0                                 ; Untyped                        ;
; BANDWIDTH_TYPE                ; AUTO                              ; Untyped                        ;
; SPREAD_FREQUENCY              ; 0                                 ; Untyped                        ;
; DOWN_SPREAD                   ; 0                                 ; Untyped                        ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                               ; Untyped                        ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                               ; Untyped                        ;
; CLK9_MULTIPLY_BY              ; 0                                 ; Untyped                        ;
; CLK8_MULTIPLY_BY              ; 0                                 ; Untyped                        ;
; CLK7_MULTIPLY_BY              ; 0                                 ; Untyped                        ;
; CLK6_MULTIPLY_BY              ; 0                                 ; Untyped                        ;
; CLK5_MULTIPLY_BY              ; 1                                 ; Untyped                        ;
; CLK4_MULTIPLY_BY              ; 1                                 ; Untyped                        ;
; CLK3_MULTIPLY_BY              ; 1                                 ; Untyped                        ;
; CLK2_MULTIPLY_BY              ; 1                                 ; Untyped                        ;
; CLK1_MULTIPLY_BY              ; 1                                 ; Untyped                        ;
; CLK0_MULTIPLY_BY              ; 6                                 ; Signed Integer                 ;
; CLK9_DIVIDE_BY                ; 0                                 ; Untyped                        ;
; CLK8_DIVIDE_BY                ; 0                                 ; Untyped                        ;
; CLK7_DIVIDE_BY                ; 0                                 ; Untyped                        ;
; CLK6_DIVIDE_BY                ; 0                                 ; Untyped                        ;
; CLK5_DIVIDE_BY                ; 1                                 ; Untyped                        ;
; CLK4_DIVIDE_BY                ; 1                                 ; Untyped                        ;
; CLK3_DIVIDE_BY                ; 1                                 ; Untyped                        ;
; CLK2_DIVIDE_BY                ; 1                                 ; Untyped                        ;
; CLK1_DIVIDE_BY                ; 1                                 ; Untyped                        ;
; CLK0_DIVIDE_BY                ; 1                                 ; Signed Integer                 ;
; CLK9_PHASE_SHIFT              ; 0                                 ; Untyped                        ;
; CLK8_PHASE_SHIFT              ; 0                                 ; Untyped                        ;
; CLK7_PHASE_SHIFT              ; 0                                 ; Untyped                        ;
; CLK6_PHASE_SHIFT              ; 0                                 ; Untyped                        ;
; CLK5_PHASE_SHIFT              ; 0                                 ; Untyped                        ;
; CLK4_PHASE_SHIFT              ; 0                                 ; Untyped                        ;
; CLK3_PHASE_SHIFT              ; 0                                 ; Untyped                        ;
; CLK2_PHASE_SHIFT              ; 0                                 ; Untyped                        ;
; CLK1_PHASE_SHIFT              ; 0                                 ; Untyped                        ;
; CLK0_PHASE_SHIFT              ; 0                                 ; Untyped                        ;
; CLK5_TIME_DELAY               ; 0                                 ; Untyped                        ;
; CLK4_TIME_DELAY               ; 0                                 ; Untyped                        ;
; CLK3_TIME_DELAY               ; 0                                 ; Untyped                        ;
; CLK2_TIME_DELAY               ; 0                                 ; Untyped                        ;
; CLK1_TIME_DELAY               ; 0                                 ; Untyped                        ;
; CLK0_TIME_DELAY               ; 0                                 ; Untyped                        ;
; CLK9_DUTY_CYCLE               ; 50                                ; Untyped                        ;
; CLK8_DUTY_CYCLE               ; 50                                ; Untyped                        ;
; CLK7_DUTY_CYCLE               ; 50                                ; Untyped                        ;
; CLK6_DUTY_CYCLE               ; 50                                ; Untyped                        ;
; CLK5_DUTY_CYCLE               ; 50                                ; Untyped                        ;
; CLK4_DUTY_CYCLE               ; 50                                ; Untyped                        ;
; CLK3_DUTY_CYCLE               ; 50                                ; Untyped                        ;
; CLK2_DUTY_CYCLE               ; 50                                ; Untyped                        ;
; CLK1_DUTY_CYCLE               ; 50                                ; Untyped                        ;
; CLK0_DUTY_CYCLE               ; 50                                ; Signed Integer                 ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                               ; Untyped                        ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                               ; Untyped                        ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                               ; Untyped                        ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                               ; Untyped                        ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                               ; Untyped                        ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                               ; Untyped                        ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                               ; Untyped                        ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                               ; Untyped                        ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                               ; Untyped                        ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                               ; Untyped                        ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                               ; Untyped                        ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                               ; Untyped                        ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                               ; Untyped                        ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                               ; Untyped                        ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                               ; Untyped                        ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                               ; Untyped                        ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                               ; Untyped                        ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                               ; Untyped                        ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                               ; Untyped                        ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                               ; Untyped                        ;
; LOCK_WINDOW_UI                ;  0.05                             ; Untyped                        ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                            ; Untyped                        ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                            ; Untyped                        ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                            ; Untyped                        ;
; DPA_MULTIPLY_BY               ; 0                                 ; Untyped                        ;
; DPA_DIVIDE_BY                 ; 1                                 ; Untyped                        ;
; DPA_DIVIDER                   ; 0                                 ; Untyped                        ;
; EXTCLK3_MULTIPLY_BY           ; 1                                 ; Untyped                        ;
; EXTCLK2_MULTIPLY_BY           ; 1                                 ; Untyped                        ;
; EXTCLK1_MULTIPLY_BY           ; 1                                 ; Untyped                        ;
; EXTCLK0_MULTIPLY_BY           ; 1                                 ; Untyped                        ;
; EXTCLK3_DIVIDE_BY             ; 1                                 ; Untyped                        ;
; EXTCLK2_DIVIDE_BY             ; 1                                 ; Untyped                        ;
; EXTCLK1_DIVIDE_BY             ; 1                                 ; Untyped                        ;
; EXTCLK0_DIVIDE_BY             ; 1                                 ; Untyped                        ;
; EXTCLK3_PHASE_SHIFT           ; 0                                 ; Untyped                        ;
; EXTCLK2_PHASE_SHIFT           ; 0                                 ; Untyped                        ;
; EXTCLK1_PHASE_SHIFT           ; 0                                 ; Untyped                        ;
; EXTCLK0_PHASE_SHIFT           ; 0                                 ; Untyped                        ;
; EXTCLK3_TIME_DELAY            ; 0                                 ; Untyped                        ;
; EXTCLK2_TIME_DELAY            ; 0                                 ; Untyped                        ;
; EXTCLK1_TIME_DELAY            ; 0                                 ; Untyped                        ;
; EXTCLK0_TIME_DELAY            ; 0                                 ; Untyped                        ;
; EXTCLK3_DUTY_CYCLE            ; 50                                ; Untyped                        ;
; EXTCLK2_DUTY_CYCLE            ; 50                                ; Untyped                        ;
; EXTCLK1_DUTY_CYCLE            ; 50                                ; Untyped                        ;
; EXTCLK0_DUTY_CYCLE            ; 50                                ; Untyped                        ;
; VCO_MULTIPLY_BY               ; 0                                 ; Untyped                        ;
; VCO_DIVIDE_BY                 ; 0                                 ; Untyped                        ;
; SCLKOUT0_PHASE_SHIFT          ; 0                                 ; Untyped                        ;
; SCLKOUT1_PHASE_SHIFT          ; 0                                 ; Untyped                        ;
; VCO_MIN                       ; 0                                 ; Untyped                        ;
; VCO_MAX                       ; 0                                 ; Untyped                        ;
; VCO_CENTER                    ; 0                                 ; Untyped                        ;
; PFD_MIN                       ; 0                                 ; Untyped                        ;
; PFD_MAX                       ; 0                                 ; Untyped                        ;
; M_INITIAL                     ; 0                                 ; Untyped                        ;
; M                             ; 0                                 ; Untyped                        ;
; N                             ; 1                                 ; Untyped                        ;
; M2                            ; 1                                 ; Untyped                        ;
; N2                            ; 1                                 ; Untyped                        ;
; SS                            ; 1                                 ; Untyped                        ;
; C0_HIGH                       ; 0                                 ; Untyped                        ;
; C1_HIGH                       ; 0                                 ; Untyped                        ;
; C2_HIGH                       ; 0                                 ; Untyped                        ;
; C3_HIGH                       ; 0                                 ; Untyped                        ;
; C4_HIGH                       ; 0                                 ; Untyped                        ;
; C5_HIGH                       ; 0                                 ; Untyped                        ;
; C6_HIGH                       ; 0                                 ; Untyped                        ;
; C7_HIGH                       ; 0                                 ; Untyped                        ;
; C8_HIGH                       ; 0                                 ; Untyped                        ;
; C9_HIGH                       ; 0                                 ; Untyped                        ;
; C0_LOW                        ; 0                                 ; Untyped                        ;
; C1_LOW                        ; 0                                 ; Untyped                        ;
; C2_LOW                        ; 0                                 ; Untyped                        ;
; C3_LOW                        ; 0                                 ; Untyped                        ;
; C4_LOW                        ; 0                                 ; Untyped                        ;
; C5_LOW                        ; 0                                 ; Untyped                        ;
; C6_LOW                        ; 0                                 ; Untyped                        ;
; C7_LOW                        ; 0                                 ; Untyped                        ;
; C8_LOW                        ; 0                                 ; Untyped                        ;
; C9_LOW                        ; 0                                 ; Untyped                        ;
; C0_INITIAL                    ; 0                                 ; Untyped                        ;
; C1_INITIAL                    ; 0                                 ; Untyped                        ;
; C2_INITIAL                    ; 0                                 ; Untyped                        ;
; C3_INITIAL                    ; 0                                 ; Untyped                        ;
; C4_INITIAL                    ; 0                                 ; Untyped                        ;
; C5_INITIAL                    ; 0                                 ; Untyped                        ;
; C6_INITIAL                    ; 0                                 ; Untyped                        ;
; C7_INITIAL                    ; 0                                 ; Untyped                        ;
; C8_INITIAL                    ; 0                                 ; Untyped                        ;
; C9_INITIAL                    ; 0                                 ; Untyped                        ;
; C0_MODE                       ; BYPASS                            ; Untyped                        ;
; C1_MODE                       ; BYPASS                            ; Untyped                        ;
; C2_MODE                       ; BYPASS                            ; Untyped                        ;
; C3_MODE                       ; BYPASS                            ; Untyped                        ;
; C4_MODE                       ; BYPASS                            ; Untyped                        ;
; C5_MODE                       ; BYPASS                            ; Untyped                        ;
; C6_MODE                       ; BYPASS                            ; Untyped                        ;
; C7_MODE                       ; BYPASS                            ; Untyped                        ;
; C8_MODE                       ; BYPASS                            ; Untyped                        ;
; C9_MODE                       ; BYPASS                            ; Untyped                        ;
; C0_PH                         ; 0                                 ; Untyped                        ;
; C1_PH                         ; 0                                 ; Untyped                        ;
; C2_PH                         ; 0                                 ; Untyped                        ;
; C3_PH                         ; 0                                 ; Untyped                        ;
; C4_PH                         ; 0                                 ; Untyped                        ;
; C5_PH                         ; 0                                 ; Untyped                        ;
; C6_PH                         ; 0                                 ; Untyped                        ;
; C7_PH                         ; 0                                 ; Untyped                        ;
; C8_PH                         ; 0                                 ; Untyped                        ;
; C9_PH                         ; 0                                 ; Untyped                        ;
; L0_HIGH                       ; 1                                 ; Untyped                        ;
; L1_HIGH                       ; 1                                 ; Untyped                        ;
; G0_HIGH                       ; 1                                 ; Untyped                        ;
; G1_HIGH                       ; 1                                 ; Untyped                        ;
; G2_HIGH                       ; 1                                 ; Untyped                        ;
; G3_HIGH                       ; 1                                 ; Untyped                        ;
; E0_HIGH                       ; 1                                 ; Untyped                        ;
; E1_HIGH                       ; 1                                 ; Untyped                        ;
; E2_HIGH                       ; 1                                 ; Untyped                        ;
; E3_HIGH                       ; 1                                 ; Untyped                        ;
; L0_LOW                        ; 1                                 ; Untyped                        ;
; L1_LOW                        ; 1                                 ; Untyped                        ;
; G0_LOW                        ; 1                                 ; Untyped                        ;
; G1_LOW                        ; 1                                 ; Untyped                        ;
; G2_LOW                        ; 1                                 ; Untyped                        ;
; G3_LOW                        ; 1                                 ; Untyped                        ;
; E0_LOW                        ; 1                                 ; Untyped                        ;
; E1_LOW                        ; 1                                 ; Untyped                        ;
; E2_LOW                        ; 1                                 ; Untyped                        ;
; E3_LOW                        ; 1                                 ; Untyped                        ;
; L0_INITIAL                    ; 1                                 ; Untyped                        ;
; L1_INITIAL                    ; 1                                 ; Untyped                        ;
; G0_INITIAL                    ; 1                                 ; Untyped                        ;
; G1_INITIAL                    ; 1                                 ; Untyped                        ;
; G2_INITIAL                    ; 1                                 ; Untyped                        ;
; G3_INITIAL                    ; 1                                 ; Untyped                        ;
; E0_INITIAL                    ; 1                                 ; Untyped                        ;
; E1_INITIAL                    ; 1                                 ; Untyped                        ;
; E2_INITIAL                    ; 1                                 ; Untyped                        ;
; E3_INITIAL                    ; 1                                 ; Untyped                        ;
; L0_MODE                       ; BYPASS                            ; Untyped                        ;
; L1_MODE                       ; BYPASS                            ; Untyped                        ;
; G0_MODE                       ; BYPASS                            ; Untyped                        ;
; G1_MODE                       ; BYPASS                            ; Untyped                        ;
; G2_MODE                       ; BYPASS                            ; Untyped                        ;
; G3_MODE                       ; BYPASS                            ; Untyped                        ;
; E0_MODE                       ; BYPASS                            ; Untyped                        ;
; E1_MODE                       ; BYPASS                            ; Untyped                        ;
; E2_MODE                       ; BYPASS                            ; Untyped                        ;
; E3_MODE                       ; BYPASS                            ; Untyped                        ;
; L0_PH                         ; 0                                 ; Untyped                        ;
; L1_PH                         ; 0                                 ; Untyped                        ;
; G0_PH                         ; 0                                 ; Untyped                        ;
; G1_PH                         ; 0                                 ; Untyped                        ;
; G2_PH                         ; 0                                 ; Untyped                        ;
; G3_PH                         ; 0                                 ; Untyped                        ;
; E0_PH                         ; 0                                 ; Untyped                        ;
; E1_PH                         ; 0                                 ; Untyped                        ;
; E2_PH                         ; 0                                 ; Untyped                        ;
; E3_PH                         ; 0                                 ; Untyped                        ;
; M_PH                          ; 0                                 ; Untyped                        ;
; C1_USE_CASC_IN                ; OFF                               ; Untyped                        ;
; C2_USE_CASC_IN                ; OFF                               ; Untyped                        ;
; C3_USE_CASC_IN                ; OFF                               ; Untyped                        ;
; C4_USE_CASC_IN                ; OFF                               ; Untyped                        ;
; C5_USE_CASC_IN                ; OFF                               ; Untyped                        ;
; C6_USE_CASC_IN                ; OFF                               ; Untyped                        ;
; C7_USE_CASC_IN                ; OFF                               ; Untyped                        ;
; C8_USE_CASC_IN                ; OFF                               ; Untyped                        ;
; C9_USE_CASC_IN                ; OFF                               ; Untyped                        ;
; CLK0_COUNTER                  ; G0                                ; Untyped                        ;
; CLK1_COUNTER                  ; G0                                ; Untyped                        ;
; CLK2_COUNTER                  ; G0                                ; Untyped                        ;
; CLK3_COUNTER                  ; G0                                ; Untyped                        ;
; CLK4_COUNTER                  ; G0                                ; Untyped                        ;
; CLK5_COUNTER                  ; G0                                ; Untyped                        ;
; CLK6_COUNTER                  ; E0                                ; Untyped                        ;
; CLK7_COUNTER                  ; E1                                ; Untyped                        ;
; CLK8_COUNTER                  ; E2                                ; Untyped                        ;
; CLK9_COUNTER                  ; E3                                ; Untyped                        ;
; L0_TIME_DELAY                 ; 0                                 ; Untyped                        ;
; L1_TIME_DELAY                 ; 0                                 ; Untyped                        ;
; G0_TIME_DELAY                 ; 0                                 ; Untyped                        ;
; G1_TIME_DELAY                 ; 0                                 ; Untyped                        ;
; G2_TIME_DELAY                 ; 0                                 ; Untyped                        ;
; G3_TIME_DELAY                 ; 0                                 ; Untyped                        ;
; E0_TIME_DELAY                 ; 0                                 ; Untyped                        ;
; E1_TIME_DELAY                 ; 0                                 ; Untyped                        ;
; E2_TIME_DELAY                 ; 0                                 ; Untyped                        ;
; E3_TIME_DELAY                 ; 0                                 ; Untyped                        ;
; M_TIME_DELAY                  ; 0                                 ; Untyped                        ;
; N_TIME_DELAY                  ; 0                                 ; Untyped                        ;
; EXTCLK3_COUNTER               ; E3                                ; Untyped                        ;
; EXTCLK2_COUNTER               ; E2                                ; Untyped                        ;
; EXTCLK1_COUNTER               ; E1                                ; Untyped                        ;
; EXTCLK0_COUNTER               ; E0                                ; Untyped                        ;
; ENABLE0_COUNTER               ; L0                                ; Untyped                        ;
; ENABLE1_COUNTER               ; L0                                ; Untyped                        ;
; CHARGE_PUMP_CURRENT           ; 2                                 ; Untyped                        ;
; LOOP_FILTER_R                 ;  1.000000                         ; Untyped                        ;
; LOOP_FILTER_C                 ; 5                                 ; Untyped                        ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                              ; Untyped                        ;
; LOOP_FILTER_R_BITS            ; 9999                              ; Untyped                        ;
; LOOP_FILTER_C_BITS            ; 9999                              ; Untyped                        ;
; VCO_POST_SCALE                ; 0                                 ; Untyped                        ;
; CLK2_OUTPUT_FREQUENCY         ; 0                                 ; Untyped                        ;
; CLK1_OUTPUT_FREQUENCY         ; 0                                 ; Untyped                        ;
; CLK0_OUTPUT_FREQUENCY         ; 0                                 ; Untyped                        ;
; INTENDED_DEVICE_FAMILY        ; MAX 10                            ; Untyped                        ;
; PORT_CLKENA0                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLKENA1                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLKENA2                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLKENA3                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLKENA4                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLKENA5                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY                 ; Untyped                        ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY                 ; Untyped                        ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY                 ; Untyped                        ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY                 ; Untyped                        ;
; PORT_EXTCLK0                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_EXTCLK1                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_EXTCLK2                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_EXTCLK3                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLKBAD0                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLKBAD1                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLK0                     ; PORT_USED                         ; Untyped                        ;
; PORT_CLK1                     ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLK2                     ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLK3                     ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLK4                     ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLK5                     ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLK6                     ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLK7                     ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLK8                     ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLK9                     ; PORT_UNUSED                       ; Untyped                        ;
; PORT_SCANDATA                 ; PORT_UNUSED                       ; Untyped                        ;
; PORT_SCANDATAOUT              ; PORT_UNUSED                       ; Untyped                        ;
; PORT_SCANDONE                 ; PORT_UNUSED                       ; Untyped                        ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY                 ; Untyped                        ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY                 ; Untyped                        ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLKLOSS                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_INCLK1                   ; PORT_UNUSED                       ; Untyped                        ;
; PORT_INCLK0                   ; PORT_USED                         ; Untyped                        ;
; PORT_FBIN                     ; PORT_UNUSED                       ; Untyped                        ;
; PORT_PLLENA                   ; PORT_UNUSED                       ; Untyped                        ;
; PORT_CLKSWITCH                ; PORT_UNUSED                       ; Untyped                        ;
; PORT_ARESET                   ; PORT_UNUSED                       ; Untyped                        ;
; PORT_PFDENA                   ; PORT_UNUSED                       ; Untyped                        ;
; PORT_SCANCLK                  ; PORT_UNUSED                       ; Untyped                        ;
; PORT_SCANACLR                 ; PORT_UNUSED                       ; Untyped                        ;
; PORT_SCANREAD                 ; PORT_UNUSED                       ; Untyped                        ;
; PORT_SCANWRITE                ; PORT_UNUSED                       ; Untyped                        ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY                 ; Untyped                        ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY                 ; Untyped                        ;
; PORT_LOCKED                   ; PORT_USED                         ; Untyped                        ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED                       ; Untyped                        ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY                 ; Untyped                        ;
; PORT_PHASEDONE                ; PORT_UNUSED                       ; Untyped                        ;
; PORT_PHASESTEP                ; PORT_UNUSED                       ; Untyped                        ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED                       ; Untyped                        ;
; PORT_SCANCLKENA               ; PORT_UNUSED                       ; Untyped                        ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED                       ; Untyped                        ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY                 ; Untyped                        ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY                 ; Untyped                        ;
; M_TEST_SOURCE                 ; 5                                 ; Untyped                        ;
; C0_TEST_SOURCE                ; 5                                 ; Untyped                        ;
; C1_TEST_SOURCE                ; 5                                 ; Untyped                        ;
; C2_TEST_SOURCE                ; 5                                 ; Untyped                        ;
; C3_TEST_SOURCE                ; 5                                 ; Untyped                        ;
; C4_TEST_SOURCE                ; 5                                 ; Untyped                        ;
; C5_TEST_SOURCE                ; 5                                 ; Untyped                        ;
; C6_TEST_SOURCE                ; 5                                 ; Untyped                        ;
; C7_TEST_SOURCE                ; 5                                 ; Untyped                        ;
; C8_TEST_SOURCE                ; 5                                 ; Untyped                        ;
; C9_TEST_SOURCE                ; 5                                 ; Untyped                        ;
; CBXI_PARAMETER                ; alt_pll_220_110_altpll            ; Untyped                        ;
; VCO_FREQUENCY_CONTROL         ; AUTO                              ; Untyped                        ;
; VCO_PHASE_SHIFT_STEP          ; 0                                 ; Untyped                        ;
; WIDTH_CLOCK                   ; 5                                 ; Signed Integer                 ;
; WIDTH_PHASECOUNTERSELECT      ; 4                                 ; Untyped                        ;
; USING_FBMIMICBIDIR_PORT       ; OFF                               ; Untyped                        ;
; DEVICE_FAMILY                 ; MAX 10                            ; Untyped                        ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                            ; Untyped                        ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                               ; Untyped                        ;
; AUTO_CARRY_CHAINS             ; ON                                ; AUTO_CARRY                     ;
; IGNORE_CARRY_BUFFERS          ; OFF                               ; IGNORE_CARRY                   ;
; AUTO_CASCADE_CHAINS           ; ON                                ; AUTO_CASCADE                   ;
; IGNORE_CASCADE_BUFFERS        ; OFF                               ; IGNORE_CASCADE                 ;
+-------------------------------+-----------------------------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component ;
+------------------------+----------------+-------------------------------------------------------+
; Parameter Name         ; Value          ; Type                                                  ;
+------------------------+----------------+-------------------------------------------------------+
; LPM_WIDTHN             ; 21             ; Signed Integer                                        ;
; LPM_WIDTHD             ; 12             ; Signed Integer                                        ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                               ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                               ;
; LPM_PIPELINE           ; 2              ; Signed Integer                                        ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                               ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                               ;
; CBXI_PARAMETER         ; lpm_divide_uft ; Untyped                                               ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                               ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                               ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                            ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                          ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                          ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                        ;
+------------------------+----------------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component ;
+------------------------+----------------+----------------------------------------------------------------+
; Parameter Name         ; Value          ; Type                                                           ;
+------------------------+----------------+----------------------------------------------------------------+
; LPM_WIDTHN             ; 21             ; Signed Integer                                                 ;
; LPM_WIDTHD             ; 12             ; Signed Integer                                                 ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_PIPELINE           ; 0              ; Untyped                                                        ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                                        ;
; MAXIMIZE_SPEED         ; 6              ; Untyped                                                        ;
; CBXI_PARAMETER         ; lpm_divide_p0r ; Untyped                                                        ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                                        ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                                        ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                                 ;
+------------------------+----------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                                                                                         ;
+-------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; Parameter Name                                  ; Value                                                                                                                                                                                                                                                                                                ; Type           ;
+-------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; lpm_type                                        ; sld_signaltap                                                                                                                                                                                                                                                                                        ; String         ;
; sld_node_info                                   ; 805334528                                                                                                                                                                                                                                                                                            ; Untyped        ;
; SLD_SECTION_ID                                  ; hdl_signaltap_0                                                                                                                                                                                                                                                                                      ; String         ;
; SLD_IP_VERSION                                  ; 6                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_IP_MINOR_VERSION                            ; 0                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_COMMON_IP_VERSION                           ; 0                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; sld_data_bits                                   ; 89                                                                                                                                                                                                                                                                                                   ; Untyped        ;
; sld_trigger_bits                                ; 89                                                                                                                                                                                                                                                                                                   ; Untyped        ;
; SLD_NODE_CRC_BITS                               ; 32                                                                                                                                                                                                                                                                                                   ; Signed Integer ;
; SLD_NODE_CRC_HIWORD                             ; 41394                                                                                                                                                                                                                                                                                                ; Signed Integer ;
; SLD_NODE_CRC_LOWORD                             ; 50132                                                                                                                                                                                                                                                                                                ; Signed Integer ;
; sld_incremental_routing                         ; 1                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_sample_depth                                ; 2048                                                                                                                                                                                                                                                                                                 ; Untyped        ;
; sld_segment_size                                ; 2048                                                                                                                                                                                                                                                                                                 ; Untyped        ;
; sld_ram_block_type                              ; AUTO                                                                                                                                                                                                                                                                                                 ; Untyped        ;
; sld_state_bits                                  ; 11                                                                                                                                                                                                                                                                                                   ; Untyped        ;
; sld_buffer_full_stop                            ; 1                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; SLD_MEM_ADDRESS_BITS                            ; 7                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_DATA_BIT_CNTR_BITS                          ; 4                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; sld_trigger_level                               ; 1                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_trigger_in_enabled                          ; 0                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; SLD_HPS_TRIGGER_IN_ENABLED                      ; 0                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_HPS_TRIGGER_OUT_ENABLED                     ; 0                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_HPS_EVENT_ENABLED                           ; 0                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_HPS_EVENT_ID                                ; 0                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; sld_advanced_trigger_entity                     ; basic,1,                                                                                                                                                                                                                                                                                             ; Untyped        ;
; sld_trigger_level_pipeline                      ; 1                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_trigger_pipeline                            ; 0                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_ram_pipeline                                ; 0                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_counter_pipeline                            ; 0                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_enable_advanced_trigger                     ; 0                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; SLD_ADVANCED_TRIGGER_1                          ; NONE                                                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_2                          ; NONE                                                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_3                          ; NONE                                                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_4                          ; NONE                                                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_5                          ; NONE                                                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_6                          ; NONE                                                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_7                          ; NONE                                                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_8                          ; NONE                                                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_9                          ; NONE                                                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_10                         ; NONE                                                                                                                                                                                                                                                                                                 ; String         ;
; sld_inversion_mask_length                       ; 292                                                                                                                                                                                                                                                                                                  ; Untyped        ;
; sld_inversion_mask                              ; 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Untyped        ;
; sld_power_up_trigger                            ; 0                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; SLD_STATE_FLOW_MGR_ENTITY                       ; state_flow_mgr_entity.vhd                                                                                                                                                                                                                                                                            ; String         ;
; sld_state_flow_use_generated                    ; 0                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_current_resource_width                      ; 1                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_attribute_mem_mode                          ; OFF                                                                                                                                                                                                                                                                                                  ; Untyped        ;
; sld_storage_qualifier_bits                      ; 89                                                                                                                                                                                                                                                                                                   ; Untyped        ;
; SLD_STORAGE_QUALIFIER_GAP_RECORD                ; 0                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_STORAGE_QUALIFIER_MODE                      ; OFF                                                                                                                                                                                                                                                                                                  ; String         ;
; SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION ; 0                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; sld_storage_qualifier_inversion_mask_length     ; 0                                                                                                                                                                                                                                                                                                    ; Untyped        ;
; SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY ; basic                                                                                                                                                                                                                                                                                                ; String         ;
; SLD_STORAGE_QUALIFIER_PIPELINE                  ; 0                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_CREATE_MONITOR_INTERFACE                    ; 0                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_USE_JTAG_SIGNAL_ADAPTER                     ; 1                                                                                                                                                                                                                                                                                                    ; Signed Integer ;
+-------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                                          ;
+-------------------------------+-------------------------------------------------------+
; Name                          ; Value                                                 ;
+-------------------------------+-------------------------------------------------------+
; Number of entity instances    ; 1                                                     ;
; Entity Instance               ; alt_pll_220_110:a_pll_220_110|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                                ;
;     -- PLL_TYPE               ; AUTO                                                  ;
;     -- PRIMARY_CLOCK          ; INCLK0                                                ;
;     -- INCLK0_INPUT_FREQUENCY ; 62500                                                 ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                                     ;
;     -- VCO_MULTIPLY_BY        ; 0                                                     ;
;     -- VCO_DIVIDE_BY          ; 0                                                     ;
+-------------------------------+-------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                                                                    ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; Instance Index ; Instance Name    ; Trigger Input Width ; Data Input Width ; Sample Depth ; Segments ; Storage Qualifier Type ; Trigger Flow Control ; Trigger Conditions ; Advanced Trigger Conditions ; Trigger In Used ; Trigger Out Used ; Power-Up Trigger Enabled ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; 0              ; auto_signaltap_0 ; 89                  ; 89               ; 2048         ; 1        ; continuous             ; sequential           ; 1                  ; 0                           ; no              ; no               ; no                       ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 133                         ;
; cycloneiii_ff         ; 99                          ;
;     ENA               ; 78                          ;
;     ENA SCLR          ; 5                           ;
;     ENA SLD           ; 11                          ;
;     plain             ; 5                           ;
; cycloneiii_lcell_comb ; 814                         ;
;     arith             ; 386                         ;
;         2 data inputs ; 106                         ;
;         3 data inputs ; 280                         ;
;     normal            ; 428                         ;
;         0 data inputs ; 35                          ;
;         1 data inputs ; 40                          ;
;         2 data inputs ; 14                          ;
;         3 data inputs ; 223                         ;
;         4 data inputs ; 116                         ;
; cycloneiii_pll        ; 1                           ;
;                       ;                             ;
; Max LUT depth         ; 53.20                       ;
; Average LUT depth     ; 33.75                       ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:10     ;
+----------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Connections to In-System Debugging Instance "auto_signaltap_0"                                                                                                                                                                                                                                                          ;
+------------------------------------------+---------------+-----------+--------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Name                                     ; Type          ; Status    ; Partition Name                 ; Netlist Type Used ; Actual Connection                                                                                                                                                                 ; Details ;
+------------------------------------------+---------------+-----------+--------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; clk_96M                                  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated|wire_pll1_clk[0]                                                                      ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[0]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_20_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[0]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_20_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[10] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[220]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[10] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[220]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[11] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[198]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[11] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[198]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[12] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[176]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[12] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[176]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[13] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[154]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[13] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[154]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[14] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[132]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[14] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[132]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[15] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[110]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[15] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[110]~_wirecell                ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[16] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[88]~_wirecell                 ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[16] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[88]~_wirecell                 ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[17] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[66]~_wirecell                 ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[17] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|selnose[66]~_wirecell                 ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[18] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[18] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[19] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[19] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[1]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_19_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[1]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_19_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[20] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[20] ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[2]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_18_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[2]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_18_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[3]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_17_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[3]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_17_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[4]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_16_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[4]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_16_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[5]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_15_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[5]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_15_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[6]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_14_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[6]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_14_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[7]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_13_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[7]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_13_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[8]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_12_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[8]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_12_result_int[13]~26_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[9]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_11_result_int[12]~24_wirecell ; N/A     ;
; div_no_pipeline:no_pipeline|quotient[9]  ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider|add_sub_11_result_int[12]~24_wirecell ; N/A     ;
; error_out                                ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_error_out_reg                                                                                                                                                   ; N/A     ;
; error_out                                ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_error_out_reg                                                                                                                                                   ; N/A     ;
; inc_div_test:inst1|clken                 ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_divider_clk_en_reg                                                                                                                                              ; N/A     ;
; inc_div_test:inst1|clken                 ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_divider_clk_en_reg                                                                                                                                              ; N/A     ;
; inc_div_test:inst1|denom[0]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[0]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[10]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[10]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[11]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[11]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[1]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; VCC                                                                                                                                                                               ; N/A     ;
; inc_div_test:inst1|denom[1]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; VCC                                                                                                                                                                               ; N/A     ;
; inc_div_test:inst1|denom[2]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[2]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[3]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; VCC                                                                                                                                                                               ; N/A     ;
; inc_div_test:inst1|denom[3]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; VCC                                                                                                                                                                               ; N/A     ;
; inc_div_test:inst1|denom[4]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[4]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[5]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[5]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[6]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[6]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[7]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[7]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[8]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[8]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[9]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|denom[9]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividsor_reg[11]~_wirecell                                                                                                                                      ; N/A     ;
; inc_div_test:inst1|numer[0]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[0]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[0]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[0]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[10]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[10]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[10]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[10]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[11]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[11]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[11]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[11]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[12]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[12]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[12]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[12]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[13]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[13]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[13]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[13]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[14]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[14]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[14]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[14]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[15]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[15]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[15]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[15]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[16]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[16]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[16]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[16]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[17]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[17]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[17]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[17]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[18]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[18]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[18]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[18]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[19]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[19]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[19]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[19]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[1]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[1]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[1]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[1]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[20]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[20]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[20]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[20]                                                                                                                                                ; N/A     ;
; inc_div_test:inst1|numer[2]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[2]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[2]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[2]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[3]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[3]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[3]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[3]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[4]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[4]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[4]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[4]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[5]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[5]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[5]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[5]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[6]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[6]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[6]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[6]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[7]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[7]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[7]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[7]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[8]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[8]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[8]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[8]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[9]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[9]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|numer[9]              ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; test_div_1:inst|S_dividend_reg[9]                                                                                                                                                 ; N/A     ;
; inc_div_test:inst1|quotient[0]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_20_result_int[13]~26_wirecell          ; N/A     ;
; inc_div_test:inst1|quotient[0]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_20_result_int[13]~26_wirecell          ; N/A     ;
; inc_div_test:inst1|quotient[10]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[31]                                ; N/A     ;
; inc_div_test:inst1|quotient[10]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[31]                                ; N/A     ;
; inc_div_test:inst1|quotient[11]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[32]                                ; N/A     ;
; inc_div_test:inst1|quotient[11]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[32]                                ; N/A     ;
; inc_div_test:inst1|quotient[12]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[33]                                ; N/A     ;
; inc_div_test:inst1|quotient[12]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[33]                                ; N/A     ;
; inc_div_test:inst1|quotient[13]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[34]                                ; N/A     ;
; inc_div_test:inst1|quotient[13]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[34]                                ; N/A     ;
; inc_div_test:inst1|quotient[14]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[35]                                ; N/A     ;
; inc_div_test:inst1|quotient[14]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[35]                                ; N/A     ;
; inc_div_test:inst1|quotient[15]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[36]                                ; N/A     ;
; inc_div_test:inst1|quotient[15]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[36]                                ; N/A     ;
; inc_div_test:inst1|quotient[16]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[37]                                ; N/A     ;
; inc_div_test:inst1|quotient[16]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[37]                                ; N/A     ;
; inc_div_test:inst1|quotient[17]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[38]                                ; N/A     ;
; inc_div_test:inst1|quotient[17]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[38]                                ; N/A     ;
; inc_div_test:inst1|quotient[18]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; inc_div_test:inst1|quotient[18]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; inc_div_test:inst1|quotient[19]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; inc_div_test:inst1|quotient[19]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; inc_div_test:inst1|quotient[1]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_19_result_int[13]~26_wirecell          ; N/A     ;
; inc_div_test:inst1|quotient[1]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_19_result_int[13]~26_wirecell          ; N/A     ;
; inc_div_test:inst1|quotient[20]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; inc_div_test:inst1|quotient[20]          ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; GND                                                                                                                                                                               ; N/A     ;
; inc_div_test:inst1|quotient[2]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_18_result_int[13]~26_wirecell          ; N/A     ;
; inc_div_test:inst1|quotient[2]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_18_result_int[13]~26_wirecell          ; N/A     ;
; inc_div_test:inst1|quotient[3]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_17_result_int[13]~26_wirecell          ; N/A     ;
; inc_div_test:inst1|quotient[3]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_17_result_int[13]~26_wirecell          ; N/A     ;
; inc_div_test:inst1|quotient[4]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_16_result_int[13]~26_wirecell          ; N/A     ;
; inc_div_test:inst1|quotient[4]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_16_result_int[13]~26_wirecell          ; N/A     ;
; inc_div_test:inst1|quotient[5]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[26]                                ; N/A     ;
; inc_div_test:inst1|quotient[5]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[26]                                ; N/A     ;
; inc_div_test:inst1|quotient[6]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[27]                                ; N/A     ;
; inc_div_test:inst1|quotient[6]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[27]                                ; N/A     ;
; inc_div_test:inst1|quotient[7]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[28]                                ; N/A     ;
; inc_div_test:inst1|quotient[7]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[28]                                ; N/A     ;
; inc_div_test:inst1|quotient[8]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[29]                                ; N/A     ;
; inc_div_test:inst1|quotient[8]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[29]                                ; N/A     ;
; inc_div_test:inst1|quotient[9]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[30]                                ; N/A     ;
; inc_div_test:inst1|quotient[9]           ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|DFFQuotient[30]                                ; N/A     ;
; inc_div_test:inst1|remain[0]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[260]~48                               ; N/A     ;
; inc_div_test:inst1|remain[0]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[260]~48                               ; N/A     ;
; inc_div_test:inst1|remain[10]            ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[270]~49                               ; N/A     ;
; inc_div_test:inst1|remain[10]            ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[270]~49                               ; N/A     ;
; inc_div_test:inst1|remain[11]            ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[271]~50                               ; N/A     ;
; inc_div_test:inst1|remain[11]            ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[271]~50                               ; N/A     ;
; inc_div_test:inst1|remain[1]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[261]~51                               ; N/A     ;
; inc_div_test:inst1|remain[1]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[261]~51                               ; N/A     ;
; inc_div_test:inst1|remain[2]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[262]~52                               ; N/A     ;
; inc_div_test:inst1|remain[2]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[262]~52                               ; N/A     ;
; inc_div_test:inst1|remain[3]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[263]~53                               ; N/A     ;
; inc_div_test:inst1|remain[3]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[263]~53                               ; N/A     ;
; inc_div_test:inst1|remain[4]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[264]~54                               ; N/A     ;
; inc_div_test:inst1|remain[4]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[264]~54                               ; N/A     ;
; inc_div_test:inst1|remain[5]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[265]~55                               ; N/A     ;
; inc_div_test:inst1|remain[5]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[265]~55                               ; N/A     ;
; inc_div_test:inst1|remain[6]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[266]~56                               ; N/A     ;
; inc_div_test:inst1|remain[6]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[266]~56                               ; N/A     ;
; inc_div_test:inst1|remain[7]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[267]~57                               ; N/A     ;
; inc_div_test:inst1|remain[7]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[267]~57                               ; N/A     ;
; inc_div_test:inst1|remain[8]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[268]~58                               ; N/A     ;
; inc_div_test:inst1|remain[8]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[268]~58                               ; N/A     ;
; inc_div_test:inst1|remain[9]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[269]~59                               ; N/A     ;
; inc_div_test:inst1|remain[9]             ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|StageOut[269]~59                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|gnd                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
; auto_signaltap_0|vcc                     ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC                                                                                                                                               ; N/A     ;
+------------------------------------------+---------------+-----------+--------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition
    Info: Processing started: Wed Sep 16 13:22:07 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fs20_01 -c fs20_01
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file fs20_01.bdf
    Info (12023): Found entity 1: fs20_01
Warning (12019): Can't analyze file -- file inc_div.vhd is missing
Warning (12019): Can't analyze file -- file lut_inc.vhd is missing
Info (12021): Found 2 design units, including 1 entities, in source file alt_pll_220_110.vhd
    Info (12022): Found design unit 1: alt_pll_220_110-SYN File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/alt_pll_220_110.vhd Line: 53
    Info (12023): Found entity 1: alt_pll_220_110 File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/alt_pll_220_110.vhd Line: 43
Warning (12019): Can't analyze file -- file lut1um.vhd is missing
Warning (12019): Can't analyze file -- file ram_1.vhd is missing
Warning (12019): Can't analyze file -- file ram_2port_1.vhd is missing
Warning (12019): Can't analyze file -- file lut_ram.vhd is missing
Info (12021): Found 2 design units, including 1 entities, in source file div_no_pipeline.vhd
    Info (12022): Found design unit 1: div_no_pipeline-SYN File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/div_no_pipeline.vhd Line: 54
    Info (12023): Found entity 1: div_no_pipeline File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/div_no_pipeline.vhd Line: 43
Info (12021): Found 2 design units, including 1 entities, in source file inc_div_test.vhd
    Info (12022): Found design unit 1: inc_div_test-SYN File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/inc_div_test.vhd Line: 56
    Info (12023): Found entity 1: inc_div_test File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/inc_div_test.vhd Line: 43
Info (12021): Found 2 design units, including 1 entities, in source file test_div_1.vhd
    Info (12022): Found design unit 1: test_div_1-Behavioral File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/test_div_1.vhd Line: 52
    Info (12023): Found entity 1: test_div_1 File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/test_div_1.vhd Line: 31
Info (12127): Elaborating entity "fs20_01" for the top level hierarchy
Info (12128): Elaborating entity "test_div_1" for hierarchy "test_div_1:inst"
Warning (10492): VHDL Process Statement warning at test_div_1.vhd(111): signal "S_error_out_reg" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/test_div_1.vhd Line: 111
Info (12128): Elaborating entity "alt_pll_220_110" for hierarchy "alt_pll_220_110:a_pll_220_110"
Info (12128): Elaborating entity "altpll" for hierarchy "alt_pll_220_110:a_pll_220_110|altpll:altpll_component" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/alt_pll_220_110.vhd Line: 139
Info (12130): Elaborated megafunction instantiation "alt_pll_220_110:a_pll_220_110|altpll:altpll_component" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/alt_pll_220_110.vhd Line: 139
Info (12133): Instantiated megafunction "alt_pll_220_110:a_pll_220_110|altpll:altpll_component" with the following parameter: File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/alt_pll_220_110.vhd Line: 139
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "1"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "6"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "62500"
    Info (12134): Parameter "intended_device_family" = "MAX 10"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=alt_pll_220_110"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_USED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "self_reset_on_loss_lock" = "OFF"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_pll_220_110_altpll.v
    Info (12023): Found entity 1: alt_pll_220_110_altpll File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_pll_220_110_altpll.v Line: 30
Info (12128): Elaborating entity "alt_pll_220_110_altpll" for hierarchy "alt_pll_220_110:a_pll_220_110|altpll:altpll_component|alt_pll_220_110_altpll:auto_generated" File: d:/intelfpga/16.1/quartus/libraries/megafunctions/altpll.tdf Line: 898
Info (12128): Elaborating entity "inc_div_test" for hierarchy "inc_div_test:inst1"
Info (12128): Elaborating entity "lpm_divide" for hierarchy "inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/inc_div_test.vhd Line: 87
Info (12130): Elaborated megafunction instantiation "inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/inc_div_test.vhd Line: 87
Info (12133): Instantiated megafunction "inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component" with the following parameter: File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/inc_div_test.vhd Line: 87
    Info (12134): Parameter "lpm_drepresentation" = "UNSIGNED"
    Info (12134): Parameter "lpm_hint" = "MAXIMIZE_SPEED=5,LPM_REMAINDERPOSITIVE=TRUE"
    Info (12134): Parameter "lpm_nrepresentation" = "UNSIGNED"
    Info (12134): Parameter "lpm_pipeline" = "2"
    Info (12134): Parameter "lpm_type" = "LPM_DIVIDE"
    Info (12134): Parameter "lpm_widthd" = "12"
    Info (12134): Parameter "lpm_widthn" = "21"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_uft.tdf
    Info (12023): Found entity 1: lpm_divide_uft File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/lpm_divide_uft.tdf Line: 25
Info (12128): Elaborating entity "lpm_divide_uft" for hierarchy "inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated" File: d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_divide.tdf Line: 148
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_0qi.tdf
    Info (12023): Found entity 1: sign_div_unsign_0qi File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/sign_div_unsign_0qi.tdf Line: 25
Info (12128): Elaborating entity "sign_div_unsign_0qi" for hierarchy "inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/lpm_divide_uft.tdf Line: 35
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_eqf.tdf
    Info (12023): Found entity 1: alt_u_div_eqf File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_u_div_eqf.tdf Line: 30
Info (12128): Elaborating entity "alt_u_div_eqf" for hierarchy "inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/sign_div_unsign_0qi.tdf Line: 35
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_t3c.tdf
    Info (12023): Found entity 1: add_sub_t3c File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/add_sub_t3c.tdf Line: 23
Info (12128): Elaborating entity "add_sub_t3c" for hierarchy "inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_t3c:add_sub_0" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_u_div_eqf.tdf Line: 47
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_u3c.tdf
    Info (12023): Found entity 1: add_sub_u3c File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/add_sub_u3c.tdf Line: 23
Info (12128): Elaborating entity "add_sub_u3c" for hierarchy "inc_div_test:inst1|lpm_divide:LPM_DIVIDE_component|lpm_divide_uft:auto_generated|sign_div_unsign_0qi:divider|alt_u_div_eqf:divider|add_sub_u3c:add_sub_1" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_u_div_eqf.tdf Line: 48
Info (12128): Elaborating entity "div_no_pipeline" for hierarchy "div_no_pipeline:no_pipeline"
Info (12128): Elaborating entity "lpm_divide" for hierarchy "div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/div_no_pipeline.vhd Line: 82
Info (12130): Elaborated megafunction instantiation "div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/div_no_pipeline.vhd Line: 82
Info (12133): Instantiated megafunction "div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component" with the following parameter: File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/div_no_pipeline.vhd Line: 82
    Info (12134): Parameter "lpm_drepresentation" = "UNSIGNED"
    Info (12134): Parameter "lpm_hint" = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE"
    Info (12134): Parameter "lpm_nrepresentation" = "UNSIGNED"
    Info (12134): Parameter "lpm_type" = "LPM_DIVIDE"
    Info (12134): Parameter "lpm_widthd" = "12"
    Info (12134): Parameter "lpm_widthn" = "21"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_p0r.tdf
    Info (12023): Found entity 1: lpm_divide_p0r File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/lpm_divide_p0r.tdf Line: 25
Info (12128): Elaborating entity "lpm_divide_p0r" for hierarchy "div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated" File: d:/intelfpga/16.1/quartus/libraries/megafunctions/lpm_divide.tdf Line: 148
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_6nh.tdf
    Info (12023): Found entity 1: sign_div_unsign_6nh File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/sign_div_unsign_6nh.tdf Line: 25
Info (12128): Elaborating entity "sign_div_unsign_6nh" for hierarchy "div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/lpm_divide_p0r.tdf Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_lke.tdf
    Info (12023): Found entity 1: alt_u_div_lke File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/alt_u_div_lke.tdf Line: 27
Info (12128): Elaborating entity "alt_u_div_lke" for hierarchy "div_no_pipeline:no_pipeline|lpm_divide:LPM_DIVIDE_component|lpm_divide_p0r:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_lke:divider" File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/sign_div_unsign_6nh.tdf Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_am14.tdf
    Info (12023): Found entity 1: altsyncram_am14 File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/altsyncram_am14.tdf Line: 28
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_h7c.tdf
    Info (12023): Found entity 1: mux_h7c File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/mux_h7c.tdf Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_3af.tdf
    Info (12023): Found entity 1: decode_3af File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/decode_3af.tdf Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_lrh.tdf
    Info (12023): Found entity 1: cntr_lrh File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_lrh.tdf Line: 28
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_jrb.tdf
    Info (12023): Found entity 1: cmpr_jrb File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cmpr_jrb.tdf Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_6ki.tdf
    Info (12023): Found entity 1: cntr_6ki File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_6ki.tdf Line: 26
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_4rh.tdf
    Info (12023): Found entity 1: cntr_4rh File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_4rh.tdf Line: 28
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_hrb.tdf
    Info (12023): Found entity 1: cmpr_hrb File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cmpr_hrb.tdf Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_odi.tdf
    Info (12023): Found entity 1: cntr_odi File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cntr_odi.tdf Line: 28
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_drb.tdf
    Info (12023): Found entity 1: cmpr_drb File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/cmpr_drb.tdf Line: 23
Info (12033): Analysis and Synthesis generated SignalTap II or debug node instance "auto_signaltap_0"
Info (11170): Starting IP generation for the debug fabric: alt_sld_fab.
Info (11172): 2020.09.16.13:22:47 Progress: Loading sld5df68646/alt_sld_fab_wrapper_hw.tcl
Info (11172): Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG
Info (11172): Alt_sld_fab: Generating alt_sld_fab "alt_sld_fab" for QUARTUS_SYNTH
Info (11172): Alt_sld_fab: "alt_sld_fab" instantiated alt_sld_fab "alt_sld_fab"
Info (11172): Presplit: "alt_sld_fab" instantiated altera_super_splitter "presplit"
Info (11172): Splitter: "alt_sld_fab" instantiated altera_sld_splitter "splitter"
Info (11172): Sldfabric: "alt_sld_fab" instantiated altera_sld_jtag_hub "sldfabric"
Info (11172): Ident: "alt_sld_fab" instantiated altera_connection_identification_hub "ident"
Info (11172): Alt_sld_fab: Done "alt_sld_fab" with 6 modules, 6 files
Info (11171): Finished IP generation for the debug fabric: alt_sld_fab.
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld5df68646/alt_sld_fab.v
    Info (12023): Found entity 1: alt_sld_fab File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/alt_sld_fab.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab.v
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_ident.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_ident File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_ident.sv Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_presplit.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_presplit File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_presplit.sv Line: 3
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd
    Info (12022): Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 102
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_splitter.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_splitter File: E:/cangzhou/20200915/fs20_01_10m08_20200827bak_test_div/db/ip/sld5df68646/submodules/alt_sld_fab_alt_sld_fab_splitter.sv Line: 3
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "quotient[20]" is stuck at GND
    Warning (13410): Pin "quotient[19]" is stuck at GND
    Warning (13410): Pin "quotient[18]" is stuck at GND
    Warning (13410): Pin "test1[20]" is stuck at GND
    Warning (13410): Pin "test1[19]" is stuck at GND
    Warning (13410): Pin "test1[18]" is stuck at GND
Info (286031): Timing-Driven Synthesis is running on partition "Top"
Info (17049): 8 registers lost all their fanouts during netlist optimizations.
Info (35024): Successfully connected in-system debug instance "auto_signaltap_0" to all 211 required data inputs, trigger inputs, acquisition clocks, and dynamic pins
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 2839 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 4 input pins
    Info (21059): Implemented 44 output pins
    Info (21061): Implemented 2700 logic cells
    Info (21064): Implemented 89 RAM segments
    Info (21065): Implemented 1 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
    Info: Peak virtual memory: 4883 megabytes
    Info: Processing ended: Wed Sep 16 13:23:24 2020
    Info: Elapsed time: 00:01:17
    Info: Total CPU time (on all processors): 00:01:43


