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-- Company: 
-- Engineer: 
-- 
-- Create Date:   
-- Design Name: 
-- Module Name:    inc_xifen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all


entity ttl_5um is
    Port ( 
			clk : in std_logic;
			addr_in : in std_logic_vector(1 downto 0);
			ttl_AB_5um:out std_logic_vector(1 downto 0)
			  
				);


end ttl_5um;


architecture Behavioral of ttl_5um is
signal S_ttl_AB_5um : std_logic_vector(1 downto 0):="00";

begin

process(clk)
begin
	if rising_edge(clk) then
		case addr_in is
			when "00"=>
				S_ttl_AB_5um<="10";
			when "01"=>
				S_ttl_AB_5um<="11";
			
			when "10"=>
				S_ttl_AB_5um<="01";
			when "11"=>
				S_ttl_AB_5um<="00";
			when others=>
				null;
		end case;		
	
	end if;
end process;

ttl_AB_5um<=S_ttl_AB_5um;


end Behavioral;
