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-- Company: 
-- Engineer: 
-- 
-- Create Date:   
-- Design Name: 
-- Module Name:    test_div_1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all


entity test_div_1 is
    Port ( clk : in  STD_LOGIC;



			  dividend : out std_logic_vector(20 downto 0);				-- shift 8bits
			  dividsor : out std_logic_vector(11 downto 0);

	  
			  quotient : in std_logic_vector(10 downto 0);
			  divider_clk_en : out std_logic;
			  error_out: out std_logic
			  
			  
			  
			  
				);


end test_div_1;

architecture Behavioral of test_div_1 is
type state is (idle,st0,st1,st2,st3,st4,st5,st6,st7,st8,st9);

-------------------reg-------------------
signal S_state_reg : state :=idle;
signal S_dividend_reg : unsigned(20 downto 0):=(others=>'0');
signal S_dividsor_reg : unsigned(11 downto 0):=(others=>'1');
--signal S_inc_lut_addr_reg : unsigned(7 downto 0):=(others=>'0');
signal S_counter_reg : unsigned(4 downto 0):=(others=>'0');
signal S_divider_clk_en_reg: std_logic:='0';
signal S_error_out_reg: std_logic:='0';
signal S_quotient_bak_reg : std_logic_vector(10 downto 0):=(others=>'0');
-------------------reg-------------------


-------------------next-------------------
signal S_state_next : state :=idle;
signal S_dividend_next : unsigned(20 downto 0):=(others=>'0');
signal S_dividsor_next : unsigned(11 downto 0):=(others=>'1');
--signal S_inc_lut_addr_next : unsigned(7 downto 0):=(others=>'0');
signal S_counter_next : unsigned(4 downto 0):=(others=>'0');
signal S_error_out_next: std_logic:='0';
signal S_quotient_bak_next : std_logic_vector(10 downto 0):=(others=>'0');
signal S_divider_clk_en_next: std_logic:='0';
-------------------reg-------------------



begin
p_reg1: process(clk)
begin
	if rising_edge(clk)then

		S_state_reg<=S_state_next;

		S_dividend_reg <=S_dividend_next;
		S_dividsor_reg <=S_dividsor_next;

		S_counter_reg<=S_counter_next;
		S_divider_clk_en_reg<=S_divider_clk_en_next;
		S_quotient_bak_reg<=S_quotient_bak_next;
		S_error_out_reg<=S_error_out_next;

	end if;


end process p_reg1;



p_reg2: process(S_state_reg,S_dividend_reg,S_dividsor_reg,
S_counter_reg,S_divider_clk_en_reg,quotient,S_quotient_bak_reg
)
begin
	 S_state_next<=S_state_reg;
	 S_dividend_next<=S_dividend_reg;
	 S_dividsor_next<=S_dividsor_reg;
	 S_counter_next<=S_counter_reg;
	 S_divider_clk_en_next<=S_divider_clk_en_reg;
	 S_error_out_next<=S_error_out_reg;
	 S_quotient_bak_next<=S_quotient_bak_reg;

	case S_state_reg is
		when idle =>
			S_dividsor_next<="000000001010";		
			S_counter_next<=(others=>'0');
			S_divider_clk_en_next<='1';
			S_dividend_next<=S_dividend_reg + 1;
			S_state_next<=st0;

		when st0=>
			if S_counter_reg=7 then				--
				S_counter_next<=(others=>'0');
				S_divider_clk_en_next<='0';				
				S_state_next<=st1;				
				
			else	
				S_counter_next<=S_counter_reg + 1;
			end if;			
			
			if S_counter_reg=3 then	
				S_quotient_bak_next<=quotient;
			
			end if;
		
		when st1 =>

			if S_counter_reg=7 then				--
				S_counter_next<=(others=>'0');
				S_state_next<=idle;				
				
			else	
				S_counter_next<=S_counter_reg + 1;
			end if;
		
			if S_quotient_bak_reg = quotient then
				
				S_error_out_next<='0';
			
			else
				S_error_out_next<='1';
			
			end if;
		
		when others =>
			null;
	end case;
end process p_reg2;


dividend<=std_logic_vector(S_dividend_reg);
dividsor<=std_logic_vector(S_dividsor_reg);
--inc_lut_addr<=S_inc_lut_addr_reg;
divider_clk_en<=S_divider_clk_en_reg;
--ttl_ab<=S_ttl_ab_reg;
error_out<=S_error_out_reg;
end Behavioral;
