/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2016  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Intel and sold by Intel or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.
*/
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(symbol
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	(text "alt_pll_220_110" (rect 84 0 189 16)(font "Arial" (font_size 10)))
	(text "inst" (rect 8 136 25 148)(font "Arial" ))
	(port
		(pt 0 64)
		(input)
		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
		(line (pt 0 64)(pt 40 64))
	)
	(port
		(pt 256 64)
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		(pt 256 80)
		(output)
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	)
	(drawing
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		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
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)
