# Copyright (C) 2016  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
# devices manufactured by Intel and sold by Intel or its 
# authorized distributors.  Please refer to the applicable 
# agreement for further details.

# Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition
# File: E:\qiaodong\FS20\fs20_01\fs20_01.csv
# Generated on: Fri Aug 14 15:23:09 2020

# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus Prime software.

To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation
clk_in_16M,Input,,,,,,,,,
cos_adc_cs,Output,,,,,,,,,
cos_adc_sclk,Output,,,,,,,,,
cos_sdo,Input,,,,,,,,,
fpga2mcu_spi_data,Output,,,,,,,,,
fpga_receive,Input,,,,,,,,,
reset_in,Input,,,,,,,,,
sin_adc_cs,Output,,,,,,,,,
sin_adc_sclk,Output,,,,,,,,,
sin_sdo,Input,,,,,,,,,
spi_clk,Input,,,,,,,,,
spi_data,Input,,,,,,,,,
ttl_ab[1],Output,,,,,,,,,
ttl_ab[0],Output,,,,,,,,,
