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Altera_Forum's avatar
Altera_Forum
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17 years ago

Location constraints StratixIIGX legacy controller

I assign the pins for I/Os as per the board requirements. In order to minimize the timing skew, the sampling registers are placed close to each other and to the serial input pin. To place the register in particular LAB, it should have some relation with pin location assignment for the serial input pin.

Is there any document available which tells the LAB location nearer to I/O pin.

Regards,

Harsh Bandil

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The LAB location can be visualized in the Floorplan view. I would expect, however, that's it's pretty easy for Quartus P&R tool to indentify the optimal register locations from timing constraints, unless you don't make confusing specifications yourself.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks FVM for reply

    With the pin assignments as per our board, i am getting timing failures in resynchronisation path. When the variation is generated, the megawizard generated the datapath constraint script which includes the constraints for IOs and also resynchronisation path. But in assignment editor, I am editing the constraint for IOs only. So I doubt that may be the reason for failure. I think constraints for resynchronisation path must also be edited with I/o constraints.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I see. If there are LAB locations constraints from the Megawizard, you may try to delete them before synthesis. It may be however the case, that your I/O location constraints are completely unsuitable for the design.