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Altera_Forum's avatar
Altera_Forum
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17 years ago

Location constraints StratixIIGX legacy controller

I assign the pins for I/Os as per the board requirements. In order to minimize the timing skew, the sampling registers are placed close to each other and to the serial input pin. To place the registe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I see. If there are LAB locations constraints from the Megawizard, you may try to delete them before synthesis. It may be however the case, that your I/O location constraints are completely unsuitable for the design.