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Altera_Forum
Honored Contributor
Honored ContributorLocation constraints StratixIIGX legacy controller
I assign the pins for I/Os as per the board requirements. In order to minimize the timing skew, the sampling registers are placed close to each other and to the serial input pin. To place the registe...
Altera_ForumHonored Contributor
Honored ContributorThanks FVM for reply
With the pin assignments as per our board, i am getting timing failures in resynchronisation path. When the variation is generated, the megawizard generated the datapath constraint script which includes the constraints for IOs and also resynchronisation path. But in assignment editor, I am editing the constraint for IOs only. So I doubt that may be the reason for failure. I think constraints for resynchronisation path must also be edited with I/o constraints.
