Forum Discussion
New ContributorIssue with Agilex 5 GTS PCIe IP in Quartus v24.3.1
Hi all,
I installed Quartus v24.3.1 to test the new SSGDMA changes and enable DMA on our FPGA. However, I couldn’t test the changes in hardware because the new Quartus version seems to have broken the PCIe IP—my computer can no longer connect to the FPGA via PCIe.
To investigate, I compiled the PCIe PIO example design in both Quartus v24.3 and v24.3.1 with upgraded IPs. Here’s what I found:
Quartus v24.3 (working version):
- lspci: shows FPGA on 06:00.0
- Computer can read PCIe configurations
Quartus v24.3.1:
- lspci doesn't detect the FPGA
- sudo dmesg | grep pcie shows errors from the FPGA PCIe port to the PCIe bus
The configuration for the PCIe IP are identical (except that one is updated to the newest IP).
Is there anyways to mitigate this issue? I'm happy to provide more details if needed.
Best,
Jack
Hi Jack,
I created a PCIe Gen3x4 PIO example design in Q24.3 then upgraded it to Q24.3.1 without any change. Before full compilation, clicked "Generate HDL" in qsys to make sure nothing wrong. After these, my ubuntu host was able to see the FPGA PCIe.
Regards,
Rong
4 Replies
RongY_alteraContributor
Hi,
Based on the ssgdma example user guide, the hardware portion is not supported yet.
Regards,
Rong
Jack_HHi RongYuan,
I was using the PCIE PIO Design example when testing above. It was working in hardware in 24.3 but not working now in 24.3.1.
Best,
Jack
- RongY_altera
Hi Jack,
I created a PCIe Gen3x4 PIO example design in Q24.3 then upgraded it to Q24.3.1 without any change. Before full compilation, clicked "Generate HDL" in qsys to make sure nothing wrong. After these, my ubuntu host was able to see the FPGA PCIe.
Regards,
Rong
- RongY_altera
If no further questions, I'll transit this case to community support. Thanks.
