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Jack_H's avatar
Jack_H
Icon for New Contributor rankNew Contributor
10 months ago
Solved

Issue with Agilex 5 GTS PCIe IP in Quartus v24.3.1

Hi all, I installed Quartus v24.3.1 to test the new SSGDMA changes and enable DMA on our FPGA. However, I couldn’t test the changes in hardware because the new Quartus version seems to have broken t...
Pcie
  • RongY_altera's avatar
    RongY_altera
    9 months ago

    Hi Jack,

    I created a PCIe Gen3x4 PIO example design in Q24.3 then upgraded it to Q24.3.1 without any change. Before full compilation, clicked "Generate HDL" in qsys to make sure nothing wrong. After these, my ubuntu host was able to see the FPGA PCIe.


    Regards,

    Rong



RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
9 months ago

If no further questions, I'll transit this case to community support. Thanks.