Intel P-Tile Avalon-MM for PCI Express Gen3 x16 write transaction in Quartus 19.3 tool for Stratix-10Dx Device

Hi,

To understand this issue further, it will be helpful if the following info is available:

1. Do you observe a similar behavior when performing a single 128 bytes write?
2. Does the same behavior happen for memory read?
3. Can you please capture the following signals to determine if there is more than one memory write TLP received? The trigger condition is the rising edge of *_sop_o.

• p0_rx_st_ready_i
• p0_rx_st_sop_o
• p0_rx_st_eop_o
• p0_rx_st_data_o
• p0_rx_st_valid_o
• p0_rx_st_empty_o
• p0_rx_st_hdr_o
• p0_rx_st_tlp_prfx_o
• p0_rx_st_bar_range_o
• p0_rx_st_tlp_abort_o
• p0_rx_par_err_o

Regards -SK

Hi,

Thanks for your support.

As mentioned, we are using Intel P-Tile AV-MM for PCI Express IP in our design. We also have DDR4 in our design which has AV-MM interface ports. So, we chose Intel P-Tile AV-MM for PCI Express IP to connect with AV-MM ports of DDR4 in qsys. Herewith I attach stp files for 128bytes write and read operation. Similarly, I have attached 64 bytes write and read for reference.

Yes, understand that you are using P Tile AV-MM for PCI Express IP. However, you can still add those AVST signals into the design, from the AVST interface it can help us understand what is the TLP packet that endpoint received.

Does the data width of the DDR 4 is also 512 bits? Just a sanity check, will it be any different if you connect to an On-chip memory (512 bits)?

Regards -SK

Hi,

Thanks for your response.

I will add AVST interface signals and update you. In our design, we have PCIe, DDR4 and OCR. Each interface has 512bits datawidth.Here PCIe BAM ports are connected to DDR4 and OCR through PCIe BAR Interpreter(Master to other interfaces) and pipeline bridge.

Sanity check is done many times and it is working properly.

By referring to the “p0_rx_st_hdr_0” signals, the length of the memory write/read TLP received is 8 DW (256 bits) not 16 DW (512 bits). It seems like the host is actually sent two TLP packets to the endpoint for 16 DW memory read or write. You might need to review the driver to confirm how it handles more than 16DW memory requests.

Header = 40000008000000FFF480000000000000

40h = Memory request with data

8h= length

F4800000h = Memory Address [63:32]

Regards -SK

Hi,

I will set this case to close-pending for now. Please do not hesitate to get back to me within the next 20-day close-pending period if more help is needed.

Regards -SK