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SSikk's avatar
SSikk
Icon for New Contributor rankNew Contributor
6 years ago

Intel P-Tile Avalon-MM for PCI Express Gen3 x16 write transaction in Quartus 19.3 tool for Stratix-10Dx Device

Our design is integrated with Intel P-Tile AV-MM for PCI Express and On Chip RAM. PCIe is configured as Gen3x16,512 bit. We are writing 64bytes into OCR (in single write) from PC over PCIe-BAM AVMM M...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

To understand this issue further, it will be helpful if the following info is available:

  1. Do you observe a similar behavior when performing a single 128 bytes write?
  2. Does the same behavior happen for memory read?
  3. Can you please capture the following signals to determine if there is more than one memory write TLP received? The trigger condition is the rising edge of *_sop_o.
  • p0_rx_st_ready_i
  • p0_rx_st_sop_o
  • p0_rx_st_eop_o
  • p0_rx_st_data_o
  • p0_rx_st_valid_o
  • p0_rx_st_empty_o
  • p0_rx_st_hdr_o
  • p0_rx_st_tlp_prfx_o
  • p0_rx_st_bar_range_o
  • p0_rx_st_tlp_abort_o
  • p0_rx_par_err_o

Regards -SK