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SSikk
New Contributor
New ContributorIntel P-Tile Avalon-MM for PCI Express Gen3 x16 write transaction in Quartus 19.3 tool for Stratix-10Dx Device
Our design is integrated with Intel P-Tile AV-MM for PCI Express and On Chip RAM. PCIe is configured as Gen3x16,512 bit. We are writing 64bytes into OCR (in single write) from PC over PCIe-BAM AVMM M...
SengKok_L_Intel
Regular Contributor
Regular ContributorYes, understand that you are using P Tile AV-MM for PCI Express IP. However, you can still add those AVST signals into the design, from the AVST interface it can help us understand what is the TLP packet that endpoint received.
Does the data width of the DDR 4 is also 512 bits? Just a sanity check, will it be any different if you connect to an On-chip memory (512 bits)?
Regards -SK
