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SSikk
New Contributor
New ContributorIntel P-Tile Avalon-MM for PCI Express Gen3 x16 write transaction in Quartus 19.3 tool for Stratix-10Dx Device
Our design is integrated with Intel P-Tile AV-MM for PCI Express and On Chip RAM. PCIe is configured as Gen3x16,512 bit. We are writing 64bytes into OCR (in single write) from PC over PCIe-BAM AVMM M...
SengKok_L_Intel
Regular Contributor
Regular ContributorBy referring to the “p0_rx_st_hdr_0” signals, the length of the memory write/read TLP received is 8 DW (256 bits) not 16 DW (512 bits). It seems like the host is actually sent two TLP packets to the endpoint for 16 DW memory read or write. You might need to review the driver to confirm how it handles more than 16DW memory requests.
Header = 40000008000000FFF480000000000000
40h = Memory request with data
8h= length
F4800000h = Memory Address [63:32]
Regards -SK
