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SSikk
New Contributor
New ContributorIntel P-Tile Avalon-MM for PCI Express Gen3 x16 write transaction in Quartus 19.3 tool for Stratix-10Dx Device
Our design is integrated with Intel P-Tile AV-MM for PCI Express and On Chip RAM. PCIe is configured as Gen3x16,512 bit. We are writing 64bytes into OCR (in single write) from PC over PCIe-BAM AVMM M...
SSikkNew Contributor
New ContributorHi,
Thanks for your response.
I will add AVST interface signals and update you. In our design, we have PCIe, DDR4 and OCR. Each interface has 512bits datawidth.Here PCIe BAM ports are connected to DDR4 and OCR through PCIe BAR Interpreter(Master to other interfaces) and pipeline bridge.
Sanity check is done many times and it is working properly.
