INtel Design Store "A10SOC Scalable Multispeed 10M-10G Ethernet Design" fails to test in system console ?

Thanks @DeshiL_Intel​ , for feedack about the missing "user guide document" problem.

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Actually I tried the design example as above, and found some problem here, so we definitely need that userr guide to move forward. Would you please take a look of this issue as well. Thanks very much //

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best reagrds

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Hi Jet,

Let's wait for Intel IT to fix the doc link so that we can checkout the user guide doc to find out is there any special guideline that we need to watch out in using this ref design.

The system console prompt timeout error which typically caused by either JTAG connection issue or Avalon MM bus stuck issue.

• For the time being, you can also try to reduce JTAG frequency to 16MHz or even 6MHz to see if it helps.
• Also pls ensure you are using the same Quartus version as the shown in ref design to avoid IP upgrade compatibility issue
• Pls check to ensure your Ethernet design is not stuck in reset
• Lastly, pls double check to ensure there is only one system console window open and you are not running other application like BTS or clock GUI or NIOS II terminal command sheel and etc to avoid JTAG congestion issue

Thanks

Regards,

dlim

Alright, it's good to know you get it working now.

Thanks.

Regards,

dlim

Hi @DeshiL_Intel​ , may I ask an additional question ?

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I see in ./hwtesting/system_console/main.tcl script, there's below command :

proc CONFIG_SFP_A_B_RATESEL {} {

puts " CONFIGURE SFP A "

reg_write 0x300000 0x4 0x1460

puts " CONFIGURE SFP B "

reg_write 0x300000 0x4 0x1660

}

what's the meaning of the Register_operation : reg_write 0x300000 0x4 0x1460 && reg_write 0x300000 0x4 0x1660 ?

Where can I find document to describe these Registers Functions in this design ? ? Do you know this ?

Thanks

/jet

Hi Jet,

User guide doc is meant to provide instruction steps to guide user on how to use the example design only while your question is more towards design implementation side.

Unfortunately there won't be any doc to describe on low level reg control for design implementation.

• It's expected for user to slowly trace the Quartus design connection and tcl script to find out what's what.
• Anyway, we don't share Max V CPLD software source code hence I don't think it's helpful for you to do the tracing either

To answer your question at high level,

• The SFP+ module should also has a PHY chip inside where user can access and configure these register.
• The SFP+ register function that you are looking at is for SFP data rate setting. SFP+ signaling rate selection, 0 <4.25 GBd, 1 > 4.25 GBd
• However, SFP+ reg access is not straight forward. I traced the design and board schematic and found out the Eth example design address 0x300000 is applied to FPGA SPI interface which is then connected to Max V CPLD on board. Finally MAX V CPLD uses I2C interface to communicate to SFP+ module.

Thanks.

Regards,

dlim

HI @DeshiL_Intel​ , Thanks for your efforst to dig more for my query. I understand.

I will check details of this example design, hope I can find more information inside. Thanks a lot

best regards

Hi Jet,

You are welcome.

Alright, I am setting this case to closure.

Feel free to file new forum thread if you still have enquiry in future.

Thanks.

Regards,

dlim