INtel Design Store "A10SOC Scalable Multispeed 10M-10G Ethernet Design" fails to test in system console ?

Hi Jet,

User guide doc is meant to provide instruction steps to guide user on how to use the example design only while your question is more towards design implementation side.

Unfortunately there won't be any doc to describe on low level reg control for design implementation.

• It's expected for user to slowly trace the Quartus design connection and tcl script to find out what's what.
• Anyway, we don't share Max V CPLD software source code hence I don't think it's helpful for you to do the tracing either

To answer your question at high level,

• The SFP+ module should also has a PHY chip inside where user can access and configure these register.
• The SFP+ register function that you are looking at is for SFP data rate setting. SFP+ signaling rate selection, 0 <4.25 GBd, 1 > 4.25 GBd
• However, SFP+ reg access is not straight forward. I traced the design and board schematic and found out the Eth example design address 0x300000 is applied to FPGA SPI interface which is then connected to Max V CPLD on board. Finally MAX V CPLD uses I2C interface to communicate to SFP+ module.

Thanks.

Regards,

dlim