How to handle the Verilog code in VHDL program

The language which I used is VHDL. But the model of DDR2 RAM is only provided Verilog by the vendor. So I need to used verilog code in the VHDL program. Two 16bits DDR2 RAM is connect to use as a 32bits DDR2 RAM.

The code is shown as follow, Is it right for the regular requirement? There maybe something wrong with it as it does seems well in the simulation in Modelsim. The DQ and DQS are alwanys in Hi Z state. Hope someone the help me with this problems. Thanks.

Testbence(VHDL)

--------------------

component generic_ddr2_sdram_rtl is

generic(

ROWBITS : integer := 13;

DATABITS : integer := 8;

COLBITS : integer := 9;

BANKBITS : integer := 2

);

port(

CK : in std_logic;

CK_N : in std_logic;

CKE : in std_logic;

CS_N : in std_logic;

RAS_N : in std_logic;

CAS_N : in std_logic;

WE_N : in std_logic;

DM_RDQS : inout std_logic_vector;

BA : in std_logic_vector;

ADDR : in std_logic_vector;

DQ : inout std_logic_vector;

DQS : inout std_logic_vector;

dqs_n : inout std_logic_vector;

rdqs_n : out std_logic_vector;

ODT : in std_logic

);

end component generic_ddr2_sdram_rtl;

....

verilogmodelGM1 : generic_ddr2_sdram_rtl

generic map(

ROWBITS => 13,

DATABITS => 8,

COLBITS => 9,

BANKBITS => 2

)

port map (

CK => mem_clk(0),

CK_N => mem_clk_n(0),

CKE => mem_cke(0),

CS_N => mem_cs_n(0),

RAS_N => mem_ras_n,

CAS_N => mem_cas_n,

WE_N => mem_we_n,

DM_RDQS => mem_dm(1 downto 0),

BA => mem_ba,

ADDR => mem_addr(12 downto 0),

DQ => mem_dq(15 downto 0),

DQS => mem_dqs(1 downto 0),

dqs_n => temp1(1 downto 0),

rdqs_n => temp2(1 downto 0),

ODT => mem_odt(0)

);

verilogmodelGM2 : generic_ddr2_sdram_rtl

generic map(

ROWBITS => 13,

DATABITS => 8,

COLBITS => 9,

BANKBITS => 2

)

port map (

CK => mem_clk(1),

CK_N => mem_clk_n(1),

CKE => mem_cke(0),

CS_N => mem_cs_n(0),

RAS_N => mem_ras_n,

CAS_N => mem_cas_n,

WE_N => mem_we_n,

DM_RDQS => mem_dm(3 downto 2),

BA => mem_ba,

ADDR => mem_addr(12 downto 0),

DQ => mem_dq(31 downto 16),

DQS => mem_dqs(3 downto 2),

dqs_n => temp1(3 downto 2),

rdqs_n => temp2(3 downto 2),

ODT => mem_odt(0)

);

...

Model from vendor(verilog)

--------------------

module generic_ddr2_sdram_rtl (

ck,

ck_n,

cke,

cs_n,

ras_n,

cas_n,

we_n,

dm_rdqs,

ba,

addr,

dq,

dqs,

dqs_n,

rdqs_n,

odt

);

...

// Declare Ports

input ck;

input ck_n;

input cke;

input cs_n;

input ras_n;

input cas_n;

input we_n;

inout [DM_BITS-1:0] dm_rdqs;

input [BA_BITS-1:0] ba;

input [ADDR_BITS-1:0] addr;

inout [DQ_BITS-1:0] dq;

inout [DQS_BITS-1:0] dqs;

inout [DQS_BITS-1:0] dqs_n;

output [DQS_BITS-1:0] rdqs_n;

input odt;