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Altera_Forum's avatar
Altera_Forum
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16 years ago

How to handle the Verilog code in VHDL program

The language which I used is VHDL. But the model of DDR2 RAM is only provided Verilog by the vendor. So I need to used verilog code in the VHDL program. Two 16bits DDR2 RAM is connect to use as a 32b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thank all of kindly helpers. The problem had been solved. Modelsim support the mixed language program exclude the AE version. As FvM said the DDR2 model can be got freely from the vendor but only with the verilog version. The code which is shown is right. Thanks