Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to handle the Verilog code in VHDL program
The language which I used is VHDL. But the model of DDR2 RAM is only provided Verilog by the vendor. So I need to used verilog code in the VHDL program. Two 16bits DDR2 RAM is connect to use as a 32b...
Altera_ForumHonored Contributor
Honored ContributorThank all of kindly helpers. The problem had been solved. Modelsim support the mixed language program exclude the AE version. As FvM said the DDR2 model can be got freely from the vendor but only with the verilog version. The code which is shown is right. Thanks
