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Altera_Forum
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16 years ago

How to handle the Verilog code in VHDL program

The language which I used is VHDL. But the model of DDR2 RAM is only provided Verilog by the vendor. So I need to used verilog code in the VHDL program. Two 16bits DDR2 RAM is connect to use as a 32b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You could try synthesising the model and producing a gate level VHDL output. It will be slower than a behavioural model but might get you out of your pickle.

There are a few translation tools out there so you might want to look at those too.

Have you paid for this model? It might be worth hassling the vendor to produce a VHDL model.

Alternatively shoot the person who bought a model that you can't simulate?