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Altera_Forum
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16 years ago

How to handle the Verilog code in VHDL program

The language which I used is VHDL. But the model of DDR2 RAM is only provided Verilog by the vendor. So I need to used verilog code in the VHDL program. Two 16bits DDR2 RAM is connect to use as a 32b...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I guess, it's the Micron model. They are free, but only provided as Verilog.

As far as I remember, Altera has a simple functional DDR2 model included with the DDR2 testbench, but I ddidn't use it and don't know, if it's true VHDL code or a wrapper to a Verilog model.