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Altera_Forum
Honored Contributor
Honored ContributorHow to handle the Verilog code in VHDL program
The language which I used is VHDL. But the model of DDR2 RAM is only provided Verilog by the vendor. So I need to used verilog code in the VHDL program. Two 16bits DDR2 RAM is connect to use as a 32b...
Altera_ForumHonored Contributor
Honored ContributorDid you verify, that the Verilog module is bound by ModelSim? I wonder, if a mixed language ModelSim license is required to use the model.
