Forum Discussion
7 Replies
- Altera_Forum
Honored Contributor
you can write an external module to do this.
But I recommend you replacing the video_sync_generator with the clocked_video_output component whose data out can be configured as parallel. clocked_video_output use a conduit end port for Video clock input, in sopc builder it's clock can be the same as sgdma, and it has a data fifo within it, so you don't need a dual clock fifo on the streaming line. - Altera_Forum
Honored Contributor
thank you,but i did not use the video_sync_generator ,just the ip of MP3 example,named lcd_panel_tpo_td043mtea1 .It drives the LTM—TRBD of DE2-70 board.but it use for the cyclone III DEVICE ,i want to modify it,but failed..
- Altera_Forum
Honored Contributor
oh, sorry~
I really have no idea with lcd_panel_tpo_td043mtea1 if you have to work with it. but the clocked_video_output is pretty good for driving vga or lcds with clocked pixel scanning interface, so if you are using such a lcd, you may try using it. - Altera_Forum
Honored Contributor
thanks for your reply,but i just used the university program ip or a hard module timing controller,so i hope you can give me an example project of using the *clocked_video_output*,thank you....friend...
- Altera_Forum
Honored Contributor
There is an simple example about how to use clocked video output and sgdma, hw and sw.
It's actually a ".7z" file, rename the ".zip" back to "7z". - Altera_Forum
Honored Contributor
I really appreciate your helping me.how can I contact with if i get a problem..I really want to be a friends of you...so.what board are you using now? cyclone III family device?I am using the cyclone II device...
- Altera_Forum
Honored Contributor
I have forgotten that, the project is on DE0 board(EP3C16F484C6).
you may modify pin connects, mega functions' device family... May be you'd better re-create a project.