General question about DDR2 megafunction IP

Question

Hello,

I am new to FPGA design and I need to use the DDR2 Megacore Controller.

I read the user guide and other documentation i found but I don't understand everything...

I have Altera PCI express board with 5 memory chips.

- 4 x Micron MT47H32M16CC-3 : 32 Meg x 16 bits

- 1 x Micron MT47H64M8CB-3 : 64 Meg x 8 bits

So, my data bus is 72 bits width.

I generate IP with megafunction wizard, I modify logic driver for the controler and I have successfuly make one write and one read in memory (data reads equals previously data writes, so good).

I have two questions:

- In the user guide, local_size can take many values (1,2,4,8). But in input of the controler, local_size is a single bit signal... How can it take a value different of 1 or 0 ??

- Address bus on the ddr2 controler is 23 bits width:

local_addr[22..21] = local_bank_addr[1..0]

local_addr[20..8] = local_row_addr[12..0]

local_addr[7..0] = local_col_addr[9..2] (because of 4:1 data rate)

I read micron chips datasheet (http://download.micron.com/pdf/datasheets/dram/ddr2/512mbddr2.pdf) but I don't understand how can i address all my memory with my local_addr bus ??

Are my 5 chips view as one single chip ? Can I adress lineary memories just like one memory ?

What are the max values for my row_addr[12..0], local_col_addr[9..0] and local_bank_addr[1..0] ??

Really, I have difficult to understand functionnality.

Thanks in advance for your help.

Fabrice.

altera_forum · Answer

I also calculated 23 address lines at the controller local bus respectively 25 at the RAM, corresonding to 32MWords (x64 or 72 bits). All mentioned RAM address lines are significant (respectively used in all combinations). You are always addressing the chips controlled by the DDR2 controller as one memory.

Regarding local size, DDR2 hasn't an burst length of 8, 4 is the only valid choice for a half-rate controller, local-size has to be always 1 for this reason, the line is set to 1 during memory accessses. This is mentioned also in the IP user guide, I think.

altera_forum · Answer

Thank you franck for your quickly answer.

So, if I understand, I can address all my ram from "000..." to "111..." (23 bits) just like one component. Ok.

Now, i understand. Data lines are 288 bits width and address lines are 23, so 8192 kWords x 288 bits equals 290 Mo. It's good.

But what did you said:

"I also calculated 23 address lines at the controller local bus respectively 25 at the RAM"

Why 25 at the ram?

Thanks for all!

Fabrice.

altera_forum · Answer

The two additional address lines used at the RAM are col_adr[1..0], cycled during x4 burst, you also mentioned them. Your calculation is correct.

altera_forum · Answer

Thanks for reply.

Do someone have stratix II pci express development kit ?

Some features are not clear. I explain:

Datasheet of dev kit say the board have 256 MB of DDRII Ram.

But on the "real" board, I have 5 chips of 64 MB each (4 x 32 Mwords of 16 bits + 1 x 64 Mwords of 8 bits). So the board has actually 320 MB ???

Moreover, when I calculate accessible data space :

- 288 bits data bus width

- 23 bits address lines (2^23 = 8192)

- 8192 x 288 bits = 288 MB....

I need help I think... :confused:

altera_forum · Answer

I think, ECC operation was assumed for the memory, then the additional memory space isn't available for data storage. The 64M x 8 chip is used as 32M x 8 only, apparently. 32M x 8 is also written in the handbook somewhere. So the choice is 288M or 256M, you can use 288 M without ECC, if you have a usage for the special word length.

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General question about DDR2 megafunction IP

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