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Altera_Forum
Honored Contributor
Honored ContributorGeneral question about DDR2 megafunction IP
Hello, I am new to FPGA design and I need to use the DDR2 Megacore Controller. I read the user guide and other documentation i found but I don't understand everything... I have Altera PC...
Altera_ForumHonored Contributor
Honored ContributorI think, it's exactly as I said: 32M x 72 = 288 MB without using ECC, accessible memory of 32M x 64 = 256 MB with ECC. The MT47H64M8CB-3 is used only half, as said in manual table 2-29: as 32Mx8, cause A[13] isn't operated by the DDR2 controller.
