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Altera_Forum's avatar
Altera_Forum
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17 years ago

General question about DDR2 megafunction IP

Hello, I am new to FPGA design and I need to use the DDR2 Megacore Controller. I read the user guide and other documentation i found but I don't understand everything... I have Altera PC...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The two additional address lines used at the RAM are col_adr[1..0], cycled during x4 burst, you also mentioned them. Your calculation is correct.