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Altera_Forum's avatar
Altera_Forum
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17 years ago

General question about DDR2 megafunction IP

Hello, I am new to FPGA design and I need to use the DDR2 Megacore Controller. I read the user guide and other documentation i found but I don't understand everything... I have Altera PC...
Altera_Forum's avatar
Altera_Forum
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17 years ago

I also calculated 23 address lines at the controller local bus respectively 25 at the RAM, corresonding to 32MWords (x64 or 72 bits). All mentioned RAM address lines are significant (respectively used in all combinations). You are always addressing the chips controlled by the DDR2 controller as one memory.

Regarding local size, DDR2 hasn't an burst length of 8, 4 is the only valid choice for a half-rate controller, local-size has to be always 1 for this reason, the line is set to 1 during memory accessses. This is mentioned also in the IP user guide, I think.