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greenlantern01's avatar
greenlantern01
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

FIFO Reset

Hello,

I am currently using DE10 Standard FPGA along with DC2390 daughter card. Using DE10 Standard to capture the ADC data from the daughter card. After capturing this data the data is forwarded to a Avalon FIFO instantiated in the Qsys. Linux is running on the DE10 standard board and I am able to capture these data samples using a C file.

I want to reset the FIFO every time I run the C file. Is there a way to reset the FIFO from the software?

Thanks in advance for your time and assistance.

Pcie

12 Replies

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    There is no api to reset the FIFO.

    However you could connect the reset signal of the IP to an exported HPS GPIO.

    You could toggle the GPIO to reset the IP using this method.


    Regards

    Jingyang, Teh


    • greenlantern01's avatar
      greenlantern01
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hello,

      Thanks for your response!

      Looks like the HPS GPIO can be controlled from the FPGA side. I want to control the HPS GPIO from the HPS and send a reset signal from the HPS to the FIFO. (Run the C file from the on-board Linux and using memory mapping send a signal from the GPIO to the reset pin of the FIFO whenever I run the C file so that I get fresh samples whenever I run the file) Is that possible?

      I was wondering if it was possible to program the HPS reset signal (h2f_reset)? Is it possible to send a reset signal from the HPS to the modules that the h2f_reset pin is connected whenever required?

      Thank you & Regards

      • greenlantern01's avatar
        greenlantern01
        Icon for Occasional Contributor rankOccasional Contributor
        2 years ago

        Okay, so I was able to reset the FIFO by creating a parallel PIO. Exported the PIO pin, exported the reset pin of the Avalon FIFO (working in dual clock mode) and then connected them in HDL. Sent a reset signal from the HPS to the PIO which resets the FIFO.

        However, there's a new problem now. The FIFO stays in reset. It doesn't accept any values after it is reset.

        How to solve this issue?

        Regards

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    The reset for the FIFO is a active low signal.

    Did you toggle back the reset back to high?


    Regards

    Jingyang, Teh



    • greenlantern01's avatar
      greenlantern01
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi,

      Yes, I tried toggling it back as well. No use. After it is reset the FIFO doesn't accept any values and can only get 0 as the FIFO output.

      Regards,

      Ronald

      • greenlantern01's avatar
        greenlantern01
        Icon for Occasional Contributor rankOccasional Contributor
        2 years ago

        I tried sending reset signals to both the pins. When I try to reset the "reset_out" pin, my code hangs.

        When I try to reset the reset_in, the FIFO resets but also doesn't accept any new values.

        What to do?

        Regards,

    • greenlantern01's avatar
      greenlantern01
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi,

      The FIFO reset is now finally working. I fixed the issue.

      I was wondering if there was a way to increase the read speed of the FIFO? We are missing out on a lot of data that is being written but is never read.

      Write Data:

      Read Data:

      Regards,

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    Glad that you managed to get the reset working.

    What was the changes that you made to get it working?


    The read and write are different because u have selected dual clock.

    The read and write rate are separate from the clock input.

    Could you check the clock for reading (rdclock) is the same as the write?

    Or you could selecte single clock so that both read and write is the same speed.


    Regards

    Jingyang, Teh


    • greenlantern01's avatar
      greenlantern01
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Added a PIO and a reset bridge to the design. The PIO is an output from the HPS and is connected to the reset bridge. The reset bridge is connected to the FIFO reset. So whenever I run the code, the FIFO resets.

      I am giving the same clock to both rdclock and wrclock. They appear same on SignalTap as well.

      If read and write rate are separate from clock input, what are they dependent on? Is the read rate dependent on how fast the C code is?

      Update:

      I tried running the FIFO in single clock mode. The results are the same.

      Thank you & Regards

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    The clock source is needed for the update of status register read and the input&output rate for the sink and source streaming.


    For AVMM Agent Read and write, the rate of add and clearing the buffer will depends on the rate in which you read and write to the buffer.


    Regards

    Jingyang, Teh


  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Regards

    Jingyang, Teh