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greenlantern01's avatar
greenlantern01
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

FIFO Reset

Hello, I am currently using DE10 Standard FPGA along with DC2390 daughter card. Using DE10 Standard to capture the ADC data from the daughter card. After capturing this data the data is forwarded to...
Pcie
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi


Glad that you managed to get the reset working.

What was the changes that you made to get it working?


The read and write are different because u have selected dual clock.

The read and write rate are separate from the clock input.

Could you check the clock for reading (rdclock) is the same as the write?

Or you could selecte single clock so that both read and write is the same speed.


Regards

Jingyang, Teh


  • greenlantern01's avatar
    greenlantern01
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Added a PIO and a reset bridge to the design. The PIO is an output from the HPS and is connected to the reset bridge. The reset bridge is connected to the FIFO reset. So whenever I run the code, the FIFO resets.

    I am giving the same clock to both rdclock and wrclock. They appear same on SignalTap as well.

    If read and write rate are separate from clock input, what are they dependent on? Is the read rate dependent on how fast the C code is?

    Update:

    I tried running the FIFO in single clock mode. The results are the same.

    Thank you & Regards