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greenlantern01's avatar
greenlantern01
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

FIFO Reset

Hello, I am currently using DE10 Standard FPGA along with DC2390 daughter card. Using DE10 Standard to capture the ADC data from the daughter card. After capturing this data the data is forwarded to...
Pcie
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi


The reset for the FIFO is a active low signal.

Did you toggle back the reset back to high?


Regards

Jingyang, Teh



  • greenlantern01's avatar
    greenlantern01
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi,

    Yes, I tried toggling it back as well. No use. After it is reset the FIFO doesn't accept any values and can only get 0 as the FIFO output.

    Regards,

    Ronald

    • greenlantern01's avatar
      greenlantern01
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      I tried sending reset signals to both the pins. When I try to reset the "reset_out" pin, my code hangs.

      When I try to reset the reset_in, the FIFO resets but also doesn't accept any new values.

      What to do?

      Regards,

  • greenlantern01's avatar
    greenlantern01
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi,

    The FIFO reset is now finally working. I fixed the issue.

    I was wondering if there was a way to increase the read speed of the FIFO? We are missing out on a lot of data that is being written but is never read.

    Write Data:

    Read Data:

    Regards,