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greenlantern01's avatar
greenlantern01
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

FIFO Reset

Hello, I am currently using DE10 Standard FPGA along with DC2390 daughter card. Using DE10 Standard to capture the ADC data from the daughter card. After capturing this data the data is forwarded to...
Pcie
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi


There is no api to reset the FIFO.

However you could connect the reset signal of the IP to an exported HPS GPIO.

You could toggle the GPIO to reset the IP using this method.


Regards

Jingyang, Teh


  • greenlantern01's avatar
    greenlantern01
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello,

    Thanks for your response!

    Looks like the HPS GPIO can be controlled from the FPGA side. I want to control the HPS GPIO from the HPS and send a reset signal from the HPS to the FIFO. (Run the C file from the on-board Linux and using memory mapping send a signal from the GPIO to the reset pin of the FIFO whenever I run the C file so that I get fresh samples whenever I run the file) Is that possible?

    I was wondering if it was possible to program the HPS reset signal (h2f_reset)? Is it possible to send a reset signal from the HPS to the modules that the h2f_reset pin is connected whenever required?

    Thank you & Regards

    • greenlantern01's avatar
      greenlantern01
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Okay, so I was able to reset the FIFO by creating a parallel PIO. Exported the PIO pin, exported the reset pin of the Avalon FIFO (working in dual clock mode) and then connected them in HDL. Sent a reset signal from the HPS to the PIO which resets the FIFO.

      However, there's a new problem now. The FIFO stays in reset. It doesn't accept any values after it is reset.

      How to solve this issue?

      Regards