Honored ContributorHere is an example that I did a while back when I was playing with the FFT/IFFT core. It was built with DSP Builder 6.1. Also it incorporates the unity gain formula highlighted in the Block floating point Application note.
One thing it highlights is the possibility of using the embedded MATLAB function to generate test vectors for your DSP Builder/ Simulink setup. Hope this helps.
Honored ContributorHi,
I'm trying to repeat your FFT scaling Matlab testbench simulation using DSP Builder and FFT megacore version 7.0 and I think the simulation results are not quite right. I'm attaching the display results of the initial_real/initial_imag and final_real/final_imag. If you can give some idea how to fix the problems, it will be helpful. Thanks, Regards, wimaxHonored ContributorHi, Wimax,
I don't believe there are any huge changes between version 6.1 and 7.0 (I believe the only difference is the Cyclone III support). It seems like you changed the design a bit (your input sine wave merely has amplitude of 5. Mine uses the full 16 bit resolution. The core only takes full precision value (it does not know how to handle decimal points). Therefore, if you are not putting in the full precision, then you might get some error. Also are you using the same 1024 streaming FFT? If not, you might need to change the input module embedded matlab block. That way the proper sop and eop signals would be generated. Hope this helps. - WZHonored ContributorHi,
FYI, I'm using the full resolution of 18 bits for data and twiddle on 1024 streaming FFT. I've updated and attached the new image with autoscale and it looks better now. The problem is the final_imag is not zero as the initial_imag. Do you have any idea what is the problem? Regards, ShaifulHonored ContributorHi,
Sorry for the delay in response. I just saw this posting today... It shouldn't be a big deal... probably some sort of rounding error due to fixed point representation... If you look at it... the dynamic range for image out is merely from 4 to -4. But the dynamic range for your real out is from 10^4 to -10^4ish area... therefore it's practically insignificant and I would not worry about it... Hope this helps...Honored ContributorHi wronghorizon,
Thanks, I did manage to solve the non-zero problem by using higher resolution. Now I'm trying to introduce complex multiplier in between the FFT and IFFT in order to control the output by modifying the original DSP BUilder FFT/IFFT Unity Gain Example (using multiply add module). Since I'm using a constant muliplier of 1 and 0 for each of the complex multiplier respectively, I'm expecting the same result as through, i.e. non-zero real and zero imag output as before. The problem now, I'm not getting the same result and both output are of the same magnitude with funny shapes. Do you have any idea? I'm attaching the new simulation together with this entry. Regards, wimaxHonored ContributorHi, Wimax,
I am sorry, but I no longer have access to the 7.0 version of DSP Builder (I have moved onto the newer version). But perhaps if you can describe what you are doing, I might be able to help. I am guessing whatever you are seeing should correspond to what you are building. You can simply run a quick test with the generated FFT matlab model if you want. Regards, -wronghorizonHonored ContributorHi wronghorizon,
If you have any 7.x version of DSP Builder, I think you can just drop the later version in place of the 7.0 version. Basically I'm trying to do complex multiplier using the multiply add module in the frequency domain, between the FFT and the inverse FFT. I'm attaching the screenshot of the multiplication part. In the time being the X and Y multiplier is constant 1 and zero respectively, so that I can get a through dummy processing of the real and imaginary signal (I'm getting the same output as the input stimulus). Later, I would like to implement a kind of windowing function inside the frequency domain, thus X and Y will be inside a ROM module. Just wondering what is the function of FIFO module? Thanks, Regards, ShaifulHonored ContributorHi, Shaiful,
The FIFO: The FFT and IFFT configurations that we are using employ block floating point. Essentially, each module produces an exponent. We need to keep track of these exponent and align them, if we want to know how much to shift to achieve the unity gain (see Appendix of the FFT user guide). Since FFT produces results earlier than the IFFT core. We have to store the exponents from the FFT core first. Once the IFFT core starts outputting data, then we can align the exponent properly with those from FFT. This is where the FIFO comes into play. As far as your actual model: I am suspecting your multiply and add module probably has some intrinsic delay (perhaps some default pipeline module). That delay is possibly throwing off your timing (i.e. your other signals: sop, eop, valid, ... etc. are now ahead of your actual data). I would suggest figuring out that intrinsic delay (by running a simulation on that block alone). Once you figure out that delay, go ahead and delay other control signals by the appropriate amount. Hope this helps...Honored ContributorHi, all!
Finally got around to upgrading my FFT/IFFT Unity Gain Example to version 8.0. This version is slightly different: 1. It seems like the FIFO behaves a little bit differently in version 8.0 (either it's always been like this and I haven't noticed it before, or the behavior changed in the 7.1 re-write). The FIFO has one cycle latency, after the assertion of read request flag, before it would output the correct data. To compensate for that effect, I had to delay the ifft_out_exp before adding it to the FIFO'ed fft_out_exp. Also to compensate for that delay, I also had to delay ifft_out_real and ifft_out_imag. 2. It seems like I was only passing 16 bit of data into the FFT core before. Therefore, I changed the input processing module a little bit... Now you can specify how many bits to use for your cosine wave inputs. Notice that if you use the whole 18 bits (as the FFT/IFFT cores), then your ifft_out_imag stays zero (unlike before). Notice that if you use less bits for the input, then you would get some noise in your ifft_out_imag. (This is probably due to the inexact rounding/truncating after each stage of butterfly -> an artifact of the block floating point format that the streaming FFT is using)... I have attached the updated model (.zip file) and also the updated screen shot (.jpg file). To use the .zip file... do the following: - Unzip the .zip file into your working directory. - In your working directory, create a DSPBuilder_myTest_import subfolder - Place the two .vhd files (the top level wrapper files for the FFT and IFFT module). - Open up myTest.mdl and regenerate the two IP cores. Enjoy!Honored ContributorMake sure to use 8.0SP1, otherwise this will error out.
-Baycool
