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Altera_Forum
Honored Contributor
19 years agoFFT/IFFT Unity Gain Example
Here is an example that I did a while back when I was playing with the FFT/IFFT core. It was built with DSP Builder 6.1. Also it incorporates the unity gain formula highlighted in the Block floating ...
Altera_Forum
Honored Contributor
17 years agoHi, all!
Finally got around to upgrading my FFT/IFFT Unity Gain Example to version 8.0. This version is slightly different: 1. It seems like the FIFO behaves a little bit differently in version 8.0 (either it's always been like this and I haven't noticed it before, or the behavior changed in the 7.1 re-write). The FIFO has one cycle latency, after the assertion of read request flag, before it would output the correct data. To compensate for that effect, I had to delay the ifft_out_exp before adding it to the FIFO'ed fft_out_exp. Also to compensate for that delay, I also had to delay ifft_out_real and ifft_out_imag. 2. It seems like I was only passing 16 bit of data into the FFT core before. Therefore, I changed the input processing module a little bit... Now you can specify how many bits to use for your cosine wave inputs. Notice that if you use the whole 18 bits (as the FFT/IFFT cores), then your ifft_out_imag stays zero (unlike before). Notice that if you use less bits for the input, then you would get some noise in your ifft_out_imag. (This is probably due to the inexact rounding/truncating after each stage of butterfly -> an artifact of the block floating point format that the streaming FFT is using)... I have attached the updated model (.zip file) and also the updated screen shot (.jpg file). To use the .zip file... do the following: - Unzip the .zip file into your working directory. - In your working directory, create a DSPBuilder_myTest_import subfolder - Place the two .vhd files (the top level wrapper files for the FFT and IFFT module). - Open up myTest.mdl and regenerate the two IP cores. Enjoy!