Hi,I am trying to create a memory test program for an old mass produced product. The FPGA is Cyclone IV EP4CGX50. I am trying to use ALTMEMPHY IP because this is what was used in the product and it has DDR2 configurations I need to use so I directly copy them since they already works.First, I download the .sof using Quartus programmer. Then when I try to download Hello World Small or Mem Test Small this is the error I am getting. As far as I can see on the forum. This is an error one gets when the Nios is already in reset. So here is my top module and qsys configurations to see if I am doing anything wrong. Simply, all I want to do is to create a memtest using altmemphy IP for DDR2. There must definitely be some people who are already experienced with this stuff.

Check the reset vectors in the NIOS 2 IP. If the reset vector points to uninitialized memory then you get these kinds of errors. I also have much less errors using the command line instead of the Eclipse tools GUI.

I didn't use ddr2 mem as reset vector or exception vector since I am going to test it. These are the configurations. I was going to say it at the beggining but I forgot while openning to topic. Also here is the proper qsys image. It seems like the first image is hard to understand.

I haven't used this DDR memory IP, but in all of my designs everything runs directly from the clk_0 instead of this sysclock output from the DDR. Maybe try connecting the clk directly to each IP. Other than that I am not sure.

Hi,May be can refer to this document 5.2.5.1. Nios® II Processor Application Executes in-place from OCRAM:https://www.intel.com/content/www/us/en/docs/programmable/683689/current/processor-application-executes-in-place-60969.htmlAlso, make sure the reset has proper connection.Thanks,Best regards,Shengp/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Do you have any further update or concern?

Failing to run on hardware Nios II | Altera Community

14 Replies

Jacob11
Occasional Contributor
3 years ago
Check the reset vectors in the NIOS 2 IP. If the reset vector points to uninitialized memory then you get these kinds of errors. I also have much less errors using the command line instead of the Eclipse tools GUI.
akaanb
New Contributor
3 years ago

I didn't use ddr2 mem as reset vector or exception vector since I am going to test it. These are the configurations. I was going to say it at the beggining but I forgot while openning to topic.

Also here is the proper qsys image. It seems like the first image is hard to understand.
- Jacob11
  Occasional Contributor
  3 years ago
  I haven't used this DDR memory IP, but in all of my designs everything runs directly from the clk_0 instead of this sysclock output from the DDR. Maybe try connecting the clk directly to each IP. Other than that I am not sure.
ShengN_altera
Super Contributor
3 years ago
Hi,

May be can refer to this document 5.2.5.1. Nios® II Processor Application Executes in-place from OCRAM:
https://www.intel.com/content/www/us/en/docs/programmable/683689/current/processor-application-executes-in-place-60969.html
Also, make sure the reset has proper connection.

Thanks,
Best regards,
Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
ShengN_altera
Super Contributor
3 years ago
Do you have any further update or concern?
- akaanb
  New Contributor
  3 years ago
  Dear Sheng,
  
  When I don't include altmemphy DDR2 IP in my design, I can create Small Hello World or any other application and it works. I see the "Hello world from Nios II!" at the nios console in eclipse. Same reset signal, clk32 as clock, same jtag uart, same on-chip ram.
  
  When I use DDR2 IP, I feed clk32 to the DDR2 IP. And it gives sysclk clock to prevent from metastability and cdc issues. So My system works with 62.5 sysclk. But nothing work. So either the system in reset or the ip in reset and doesn't give clock. I gave fixed '1' in top module since it is an active low reset and nothing changed. I changed it to '0' and nothing changed. I tried to do the same thing with sopcbuilder since it connects reset signals itself and nothing changed.
  
  I checked the external clock and reset circuit. It is ok. Simple push button reset that connects the pin to the ground when clicked. Otherwise pulled-up to 3.3V. Clock signal is fixed 32.768 Mhz.
  
  I share my pin assignments because there must be something that causes the IP to behave like that. I also share my top module.
  
  Should I open a premium support account? Altera FPGAs are used in a lot of old design like this one.
  
  Thanks in advance.
  Best Regards.
  DDR2_Test_5.vhd5 KB
ShengN_altera
Super Contributor
3 years ago
Hi @akaanb ,

If you want to boot with XIP from OCRAM, don't need to include the external RAM in platform designer. The external RAM only included when other boot method is used check this document https://www.intel.com/content/www/us/en/docs/programmable/683689/current/processor-booting-methods.html (page 230 onwards):

Booting from On-Chip Memory (OCRAM):

Make sure onchip memory (OCRAM) is added into your Platform Designer system.

Booting from On-Chip Flash (UFM):

Booting from EPCQ Flash:

Booting from QSPI Flash:

Booting from CFI Flash:

Make sure external RAM or onchip memory (OCRAM) is added into your Platform

Designer system.

Thanks,

Best regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
akaanb
New Contributor
3 years ago
Dear Sheng,

I have to include external ram because that is the memory I am trying to test to see if it has any issues or not. Kindly, take a look at my first message.

Thanks in advance.
Best Regards.
ShengN_altera
Super Contributor
3 years ago
Hi @akaanb ,

Then you have to use other boot method as mentioned before. May be boot from on-chip flash check this link https://www.intel.com/content/www/us/en/docs/programmable/683689/current/processor-booting-from-on-chip-flash-ufm.html then replace the on-chip memory (OCRAM) with external ram (DDR2).

Example design from Design Store:

https://www.intel.com/content/www/us/en/design-example/714513/max-10-boot-from-on-chip-flash.html

Thanks,

Best Regards,

Sheng
- akaanb
  New Contributor
  3 years ago
  Dear Sheng,
  
  Okay but I don't want to boot from on-chip flash. Product already has an external flash and uses Cyclone IV(as far as I can see it doesn't have an internal flash). We normally use sof and elf file to create a jic file and use it to program flash. But like I said, this application will be used only for repairing and product test purposes. So I power-up the FPGA and then use .sof file to program. After that I build the small mem test application using .sopcinfo file and build the software project. Then I click run-on-hardware to download my program.
  
  You can quickly check this video to understand my process: https://www.youtube.com/watch?v=oFR4KKOasG4
  
  So all my process is static and I don't want to download FPGA sof and software elf to flash because this is 1-run test. It is okay that it won't run when we power-off and power-on again.
  
  Please correct me if any of my expectations are wrong.
  
  Best Regards.
  Thanks in advance.
ShengN_altera
Super Contributor
3 years ago
Hi,

Based on video https://www.youtube.com/watch?v=oFR4KKOasG4, there is no external RAM being added in the platform designer. If boot with XIP from OCRAM, you can't have external RAM in platform designer. There are still other booting methods available which can have external RAM added - Booting from EPCQ Flash, Booting from QSPI Flash, Booting from CFI Flash and you may choose one suits you the best. These are so far I can suggest you.

Thanks,
Best Regards,
Sheng
ShengN_altera
Super Contributor
3 years ago
Hi @akaanb ,

Do you have any further concern or consideration?

Let me know if there's any.

Thanks,

Best regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
ShengN_altera
Super Contributor
3 years ago
As we do not receive any response from you on the previous question/reply/answer that we have provided, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com', view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.