akaanb
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Re: Failing to run on hardware Nios II
Dear Sheng, Okay but I don't want to boot from on-chip flash. Product already has an external flash and uses Cyclone IV(as far as I can see it doesn't have an internal flash). We normally use sof and elf file to create a jic file and use it to program flash. But like I said, this application will be used only for repairing and product test purposes. So I power-up the FPGA and then use .sof file to program. After that I build the small mem test application using .sopcinfo file and build the software project. Then I click run-on-hardware to download my program. You can quickly check this video to understand my process: https://www.youtube.com/watch?v=oFR4KKOasG4 So all my process is static and I don't want to download FPGA sof and software elf to flash because this is 1-run test. It is okay that it won't run when we power-off and power-on again. Please correct me if any of my expectations are wrong. Best Regards. Thanks in advance.Re: Failing to run on hardware Nios II
Dear Sheng, When I don't include altmemphy DDR2 IP in my design, I can create Small Hello World or any other application and it works. I see the "Hello world from Nios II!" at the nios console in eclipse. Same reset signal, clk32 as clock, same jtag uart, same on-chip ram. When I use DDR2 IP, I feed clk32 to the DDR2 IP. And it gives sysclk clock to prevent from metastability and cdc issues. So My system works with 62.5 sysclk. But nothing work. So either the system in reset or the ip in reset and doesn't give clock. I gave fixed '1' in top module since it is an active low reset and nothing changed. I changed it to '0' and nothing changed. I tried to do the same thing with sopcbuilder since it connects reset signals itself and nothing changed. I checked the external clock and reset circuit. It is ok. Simple push button reset that connects the pin to the ground when clicked. Otherwise pulled-up to 3.3V. Clock signal is fixed 32.768 Mhz. I share my pin assignments because there must be something that causes the IP to behave like that. I also share my top module. Should I open a premium support account? Altera FPGAs are used in a lot of old design like this one. Thanks in advance. Best Regards.Re: Failing to run on hardware Nios II
I didn't use ddr2 mem as reset vector or exception vector since I am going to test it. These are the configurations. I was going to say it at the beggining but I forgot while openning to topic. Also here is the proper qsys image. It seems like the first image is hard to understand.Failing to run on hardware Nios II
Hi, I am trying to create a memory test program for an old mass produced product. The FPGA is Cyclone IV EP4CGX50. I am trying to use ALTMEMPHY IP because this is what was used in the product and it has DDR2 configurations I need to use so I directly copy them since they already works. First, I download the .sof using Quartus programmer. Then when I try to download Hello World Small or Mem Test Small this is the error I am getting. As far as I can see on the forum. This is an error one gets when the Nios is already in reset. So here is my top module and qsys configurations to see if I am doing anything wrong. Simply, all I want to do is to create a memtest using altmemphy IP for DDR2. There must definitely be some people who are already experienced with this stuff.
