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akaanb's avatar
akaanb
Icon for New Contributor rankNew Contributor
3 years ago

Failing to run on hardware Nios II

Hi, I am trying to create a memory test program for an old mass produced product. The FPGA is Cyclone IV EP4CGX50. I am trying to use ALTMEMPHY IP because this is what was used in the product and ...
akaanb's avatar
akaanb
Icon for New Contributor rankNew Contributor
3 years ago

 
I didn't use ddr2 mem as reset vector or exception vector since I am going to test it. These are the configurations. I was going to say it at the beggining but I forgot while openning to topic.

Also here is the proper qsys image. It seems like the first image is hard to understand.

  • Jacob11's avatar
    Jacob11
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    I haven't used this DDR memory IP, but in all of my designs everything runs directly from the clk_0 instead of this sysclock output from the DDR. Maybe try connecting the clk directly to each IP. Other than that I am not sure.