yanghao1
New Contributor
New ContributorF-Tile Serial Lite IV simulate 仿真
Hi,
My design includes a f-tile serial lite iv ip and a system pll ip for it. When I try to run simulation for the design. The system pll's output port lock is dash line, and no clk out from pll ip.
I know that the system pll ip cannot be simulated as standalone. But in my case, i connect it to the slite, but still dont work.
Hi,
Try with the example design first.
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User...
Thank you,
Kshitij Goel
